| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra20-usb-phy.yaml | 62 - const: pll_u
66 - const: pll_u
71 - const: pll_u
76 - const: pll_u
270 - const: pll_u
286 - const: pll_u
312 - const: pll_u
316 - const: pll_u
340 clock-names = "reg", "pll_u", "utmi-pads";
368 clock-names = "reg", "pll_u", "ulpi-link";
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| /linux-6.12.1/drivers/usb/phy/ |
| D | phy-tegra-usb.c | 913 clk_disable_unprepare(phy->pll_u); in tegra_usb_phy_shutdown()
1070 err = clk_prepare_enable(phy->pll_u); in tegra_usb_phy_init()
1074 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u)); in tegra_usb_phy_init()
1082 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n", in tegra_usb_phy_init()
1119 clk_disable_unprepare(phy->pll_u); in tegra_usb_phy_init()
1393 tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u"); in tegra_usb_phy_probe()
1394 err = PTR_ERR_OR_ZERO(tegra_phy->pll_u); in tegra_usb_phy_probe()
1396 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err); in tegra_usb_phy_probe()
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| /linux-6.12.1/include/linux/usb/ |
| D | tegra_usb_phy.h | 65 struct clk *pll_u; member
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-tegra114.c | 828 { .con_id = "pll_u", .dt_id = TEGRA114_CLK_PLL_U },
947 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra114_pll_init()
952 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", in tegra114_pll_init()
958 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", in tegra114_pll_init()
963 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", in tegra114_pll_init()
968 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", in tegra114_pll_init()
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| D | clk-tegra124.c | 954 { .con_id = "pll_u", .dt_id = TEGRA124_CLK_PLL_U },
1148 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra124_pll_init()
1150 clk_register_clkdev(clk, "pll_u", NULL); in tegra124_pll_init()
1154 clk = clk_register_gate(NULL, "pll_u_480M", "pll_u", in tegra124_pll_init()
1161 clk = clk_register_fixed_factor(NULL, "pll_u_60M", "pll_u", in tegra124_pll_init()
1167 clk = clk_register_fixed_factor(NULL, "pll_u_48M", "pll_u", in tegra124_pll_init()
1173 clk = clk_register_fixed_factor(NULL, "pll_u_12M", "pll_u", in tegra124_pll_init()
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| D | clk-tegra20.c | 430 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
663 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
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| D | clk-tegra30.c | 549 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
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| D | clk-tegra210.c | 1373 pr_warn("PLL_U already enabled. Postponing set full defaults\n"); in tegra210_pllu_set_defaults()
2579 { .con_id = "pll_u", .dt_id = TEGRA210_CLK_PLL_U },
2905 pr_err("Unknown PLL_U reference frequency %lu\n", pll_ref_freq); in tegra210_enable_pllu()
2934 pr_err("Timed out waiting for PLL_U to lock\n"); in tegra210_enable_pllu()
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| /linux-6.12.1/arch/arm/boot/dts/nvidia/ |
| D | tegra20.dtsi | 872 clock-names = "reg", "pll_u", "timer", "utmi-pads";
911 clock-names = "reg", "pll_u", "ulpi-link";
943 clock-names = "reg", "pll_u", "timer", "utmi-pads";
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| D | tegra30.dtsi | 1134 clock-names = "reg", "pll_u", "utmi-pads";
1177 clock-names = "reg", "pll_u", "utmi-pads";
1219 clock-names = "reg", "pll_u", "utmi-pads";
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| D | tegra124.dtsi | 1089 clock-names = "reg", "pll_u", "utmi-pads";
1129 clock-names = "reg", "pll_u", "utmi-pads";
1168 clock-names = "reg", "pll_u", "utmi-pads";
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| D | tegra114.dtsi | 746 clock-names = "reg", "pll_u", "utmi-pads";
786 clock-names = "reg", "pll_u", "utmi-pads";
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| /linux-6.12.1/arch/arm64/boot/dts/nvidia/ |
| D | tegra132.dtsi | 1020 clock-names = "reg", "pll_u", "utmi-pads";
1061 clock-names = "reg", "pll_u", "utmi-pads";
1101 clock-names = "reg", "pll_u", "utmi-pads";
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| D | tegra210.dtsi | 1888 clock-names = "reg", "pll_u", "utmi-pads";
1926 clock-names = "reg", "pll_u", "utmi-pads";
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