| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun6i-a31-pll6-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun6i-a31-pll6-clk.yaml#
23 const: allwinner,sun6i-a31-pll6-clk
47 compatible = "allwinner,sun6i-a31-pll6-clk";
50 clock-output-names = "pll6", "pll6x2";
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| D | allwinner,sun4i-a10-pll6-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll6-clk.yaml#
23 const: allwinner,sun4i-a10-pll6-clk
47 compatible = "allwinner,sun4i-a10-pll6-clk";
50 clock-output-names = "pll6_sata", "pll6_other", "pll6";
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| D | allwinner,sun4i-a10-mbus-clk.yaml | 50 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
59 clocks = <&osc24M>, <&pll6 1>, <&pll5>;
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| D | allwinner,sun4i-a10-usb-clk.yaml | 116 clocks = <&pll6 1>;
126 clocks = <&pll6 1>;
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| D | allwinner,sun4i-a10-apb1-clk.yaml | 48 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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| D | allwinner,sun5i-a13-ahb-clk.yaml | 48 clocks = <&axi>, <&cpu>, <&pll6 1>;
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| D | allwinner,sun4i-a10-mmc-clk.yaml | 71 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| D | allwinner,sun4i-a10-mod0-clk.yaml | 67 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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| D | allwinner,sun4i-a10-ahb-clk.yaml | 95 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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| /linux-6.12.1/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 259 * can work at speeds up to 300M, just after reparenting to pll6 in sun5i_a13_get_ahb_factors()
284 * if parent is pll6, then
285 * parent_rate = pll6 rate / (m + 1)
301 /* calculate pre-divider if parent is pll6 */ in sun6i_get_ahb1_factors()
331 /* apply pre-divider first if parent is pll6 */ in sun6i_ahb1_recalc()
908 { .fixed = 4 }, /* pll6 / 4, used as ahb input */
1110 CLK_OF_DECLARE(sun4i_pll6, "allwinner,sun4i-a10-pll6-clk",
1117 CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk",
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| D | clk-factors.c | 195 * some factor clocks, such as pll5 and pll6, may have multiple in __sunxi_factors_register()
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| /linux-6.12.1/Documentation/devicetree/bindings/ata/ |
| D | allwinner,sun4i-a10-ahci.yaml | 45 clocks = <&pll6 0>, <&ahb_gates 25>;
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| /linux-6.12.1/drivers/clk/renesas/ |
| D | r8a779f0-cpg-mssr.c | 65 DEF_GEN4_PLL_V9_24(".pll6", 6, CLK_PLL6, CLK_MAIN),
179 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
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| D | r8a779h0-cpg-mssr.c | 78 DEF_GEN4_PLL_V8_25(".pll6", 6, CLK_PLL6, CLK_MAIN),
247 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
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| D | r8a779g0-cpg-mssr.c | 75 DEF_GEN4_PLL_V8_25(".pll6", 6, CLK_PLL6, CLK_MAIN),
250 * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
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| D | r9a08g045-cpg.c | 123 static const char * const sel_sdhi[] = { ".pll2_div2", ".pll6", ".pll2_div6" };
140 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
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| D | r9a07g044-cpg.c | 110 static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
137 DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
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| /linux-6.12.1/drivers/clk/ |
| D | clk-milbeaut.c | 23 #define M10V_PLL6 "pll6"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 259 #define PLL6 250 macro
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| D | qcom,gcc-msm8960.h | 291 #define PLL6 283 macro
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| D | qcom,gcc-mdm9615.h | 293 #define PLL6 283 macro
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 209 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-vf610.c | 82 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
224 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); in vf610_clocks_init()
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| D | clk-imx6sll.c | 28 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
128 …hws[IMX6SLL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, … in imx6sll_clocks_init()
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| D | clk-imx6sl.c | 69 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
222 hws[IMX6SL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3); in imx6sl_clocks_init()
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