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/linux-6.12.1/drivers/clk/mediatek/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
25 #define CON0_ISO_EN BIT(1)
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
43 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
49 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
29 #define INTEL_CX0_LANE1 BIT(1)
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
46 hweight8(lane_mask) != 1)) in lane_mask_to_lane()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
61 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
159 #define PLLSS_EN_DITHER 1
196 #define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP BIT(1)
207 #define UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE BIT(1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
[all …]
/linux-6.12.1/drivers/media/i2c/
Dccs-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/ccs-pll.c
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
8 * Copyright (C) 2011--2012 Nokia Corporation
17 #include "ccs-pll.h"
22 return max_t(u32, 1, a & ~1); in clk_div_even()
28 if (a == 1) in clk_div_even_up()
29 return 1; in clk_div_even_up()
30 return (a + 1) & ~1; in clk_div_even_up()
35 if (a == 1) in is_one_or_even()
[all …]
/linux-6.12.1/drivers/video/fbdev/aty/
Dmach64_ct.c1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
62 * are 1,2,4,8 and for some clocks other values are available too.
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
[all …]
/linux-6.12.1/drivers/clk/baikal-t1/
Dccu-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
33 #define CCU_PLL_CTL_RST BIT(1)
49 ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
51 ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
53 ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
55 ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
[all …]
/linux-6.12.1/drivers/clk/rockchip/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
[all …]
/linux-6.12.1/arch/mips/ath79/
Dclock.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
17 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/ath79-clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
[all …]
/linux-6.12.1/drivers/clk/meson/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
[all …]
/linux-6.12.1/drivers/clk/sprd/
Dpll.c1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
[all …]
/linux-6.12.1/drivers/clk/bcm/
Dclk-iproc-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
[all …]
Dclk-iproc-armpll.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
72 if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT)) in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
101 * - 25 MHz Crystal
[all …]
/linux-6.12.1/drivers/clk/imx/
Dclk-fracn-gppll.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
20 #define CLKMUX_EN BIT(1)
81 PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
83 PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
84 PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
85 PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
86 PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
87 PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
88 PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
[all …]
Dclk-pll14xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
10 #include <linux/clk-provider.h>
50 PLL_1416X_RATE(1500000000U, 375, 3, 1),
51 PLL_1416X_RATE(1400000000U, 350, 3, 1),
52 PLL_1416X_RATE(1200000000U, 300, 3, 1),
53 PLL_1416X_RATE(1000000000U, 250, 3, 1),
54 PLL_1416X_RATE(800000000U, 200, 3, 1),
63 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
92 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
[all …]
Dclk-pllv3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
33 * struct clk_pllv3 - IMX PLL clock version 3
35 * @base: base address of PLL registers
36 * @power_bit: pll power bit mask
37 * @powerup_set: set power_bit to power up the PLL
44 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
63 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
65 /* No need to wait for lock when pll is not powered up */ in clk_pllv3_wait_lock()
[all …]
/linux-6.12.1/drivers/clk/sophgo/
Dclk-cv18xx-pll.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-pll.h"
36 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_recalc_rate() local
39 value = readl(pll->common.base + pll->pll_reg); in ipll_recalc_rate()
58 for_each_pll_limit_range(pre, &limit->pre_div) { in ipll_find_rate()
59 for_each_pll_limit_range(div, &limit->div) { in ipll_find_rate()
60 for_each_pll_limit_range(post, &limit->post_div) { in ipll_find_rate()
66 if ((trate - tmp) < (trate - best_rate)) { in ipll_find_rate()
85 return -EINVAL; in ipll_find_rate()
[all …]
/linux-6.12.1/drivers/clk/at91/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
15 #define PLL_STATUS_MASK(id) (1 << (1 + (id)))
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
24 #define PLL_MUL_MAX(layout) (PLL_MUL_MASK(layout) + 1)
30 #define PLL_MAX_ID 1
52 return status & PLL_STATUS_MASK(id) ? 1 : 0; in clk_pll_ready()
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
21 #define PLL_BYPASSNL BIT(1)
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
[all …]
Dclk-alpha-pll.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
18 # define PLL_BYPASSNL BIT(1)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8996.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
33 /* pll mmio base */
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
[all …]
Dhdmi_phy_8998.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
35 /* pll mmio base */
80 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8998 *pll) in pll_get_phy() argument
82 return platform_get_drvdata(pll->pdev); in pll_get_phy()
85 static inline void hdmi_pll_write(struct hdmi_pll_8998 *pll, int offset, in hdmi_pll_write() argument
88 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
91 static inline u32 hdmi_pll_read(struct hdmi_pll_8998 *pll, int offset) in hdmi_pll_read() argument
93 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
96 static inline void hdmi_tx_chan_write(struct hdmi_pll_8998 *pll, int channel, in hdmi_tx_chan_write() argument
[all …]
/linux-6.12.1/drivers/gpu/drm/sprd/
Dmegacores_pll.c1 // SPDX-License-Identifier: GPL-2.0
16 #define H 1
18 #define DATA 1
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
30 static int dphy_calc_pll_param(struct dphy_pll *pll) in dphy_calc_pll_param() argument
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
[all …]
/linux-6.12.1/drivers/gpu/drm/omapdrm/dss/
Dvideo-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
18 struct dss_pll pll; member
30 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
35 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
40 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
43 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, in dss_dpll_power_enable()
46 msleep(1); in dss_dpll_power_enable()
51 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
54 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
[all …]
/linux-6.12.1/drivers/video/fbdev/omap2/omapfb/dss/
Dvideo-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
20 struct dss_pll pll; member
32 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
37 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
42 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
45 * DRA7x PLL CTRL's PLL_PWR_STATUS seems to always return 0, in dss_dpll_power_enable()
48 msleep(1); in dss_dpll_power_enable()
53 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
56 static int dss_video_pll_enable(struct dss_pll *pll) in dss_video_pll_enable() argument
58 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable()
[all …]
/linux-6.12.1/drivers/clk/mxs/
Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
14 * struct clk_pll - mxs pll clock
15 * @hw: clk_hw for the pll
16 * @base: base address of the pll
18 * @rate: the clock rate of the pll
20 * The mxs pll is a fixed rate clock with power and gate control,
34 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
36 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
45 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_unprepare() local
[all …]

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