| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-pll.h"
35 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
37 return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0; in mtk_pll_is_prepared()
40 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
43 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
49 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
50 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
52 pcwfbits = pcwbits - ibits; in __mtk_pll_recalc_rate()
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy.c | 1 // SPDX-License-Identifier: MIT
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
122 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_clear_response_ready_flag()
124 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane), in intel_clear_response_ready_flag()
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-alpha-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021, 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
9 #include <linux/clk-provider.h>
13 #include "clk-alpha-pll.h"
16 #define PLL_MODE(p) ((p)->offset + 0x0)
36 #define PLL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
37 #define PLL_CAL_L_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
38 #define PLL_ALPHA_VAL(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
39 #define PLL_ALPHA_VAL_U(p) ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
41 #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
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| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/clk-provider.h>
17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
47 * de-asserting the reset. Delay 10us just to be safe. in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
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| /linux-6.12.1/drivers/clk/sprd/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-pllv3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
33 * struct clk_pllv3 - IMX PLL clock version 3
35 * @base: base address of PLL registers
36 * @power_bit: pll power bit mask
37 * @powerup_set: set power_bit to power up the PLL
44 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
61 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
63 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
65 /* No need to wait for lock when pll is not powered up */ in clk_pllv3_wait_lock()
[all …]
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| D | clk-pllv4.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk-provider.h>
19 /* PLL Control Status Register (xPLLCSR) */
24 /* PLL Configuration Register (xPLLCFG) */
30 /* PLL Numerator Register (xPLLNUM) */
34 /* PLL Denominator Register (xPLLDENOM) */
50 /* Valid PLL MULT Table */
53 /* Valid PLL MULT range, (max, min) */
60 static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll) in clk_pllv4_wait_lock() argument
64 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, in clk_pllv4_wait_lock()
[all …]
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| D | clk-pll14xx.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
10 #include <linux/clk-provider.h>
92 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
94 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
97 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
123 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */ in pll1443x_calc_kdiv()
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
129 static void imx_pll14xx_calc_settings(struct clk_pll14xx *pll, unsigned long rate, in imx_pll14xx_calc_settings() argument
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| D | clk-fracn-gppll.c | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
125 imx_get_pll_settings(struct clk_fracn_gppll *pll, unsigned long rate) in imx_get_pll_settings() argument
127 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
130 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
140 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); in clk_fracn_gppll_round_rate() local
141 const struct imx_fracn_gppll_rate_table *rate_table = pll->rate_table; in clk_fracn_gppll_round_rate()
145 for (i = 0; i < pll->rate_count; i++) in clk_fracn_gppll_round_rate()
150 return rate_table[pll->rate_count - 1].rate; in clk_fracn_gppll_round_rate()
155 struct clk_fracn_gppll *pll = to_clk_fracn_gppll(hw); in clk_fracn_gppll_recalc_rate() local
[all …]
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| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
19 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
20 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
24 /* number of delay loops waiting for PLL to lock */
75 struct iproc_pll *pll; member
90 return -EINVAL; in pll_calc_param()
92 residual = target_rate - (ndiv_int * parent_rate); in pll_calc_param()
102 vco_out->ndiv_int = ndiv_int; in pll_calc_param()
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| D | clk-iproc-armpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include "clk-iproc.h"
66 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
71 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
80 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
84 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
88 pr_debug("%s: fid override %u->%u\n", __func__, fid, in __get_fid()
101 * - 25 MHz Crystal
102 * - System clock
[all …]
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| /linux-6.12.1/drivers/clk/meson/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
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| /linux-6.12.1/drivers/media/i2c/ |
| D | ccs-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/i2c/ccs-pll.c
5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
8 * Copyright (C) 2011--2012 Nokia Corporation
17 #include "ccs-pll.h"
55 dev_dbg(dev, "%s_%s out of bounds: %d (%d--%d)\n", prefix, in bounds_check()
58 return -EINVAL; in bounds_check()
78 static void print_pll(struct device *dev, struct ccs_pll *pll) in print_pll() argument
85 { &pll->vt_fr, &pll->vt_bk, PLL_VT }, in print_pll()
86 { &pll->op_fr, &pll->op_bk, PLL_OP } in print_pll()
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| D | aptina-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Aptina Sensor PLL Configuration
13 #include "aptina-pll.h"
17 struct aptina_pll *pll) in aptina_pll_calculate() argument
26 dev_dbg(dev, "PLL: ext clock %u pix clock %u\n", in aptina_pll_calculate()
27 pll->ext_clock, pll->pix_clock); in aptina_pll_calculate()
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
31 dev_err(dev, "pll: invalid external clock frequency.\n"); in aptina_pll_calculate()
32 return -EINVAL; in aptina_pll_calculate()
[all …]
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| /linux-6.12.1/drivers/clk/rockchip/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Xing Zheng <zhengxing@rock-chips.com>
14 #include <linux/clk-provider.h>
51 struct rockchip_clk_pll *pll, unsigned long rate) in rockchip_get_pll_settings() argument
53 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
56 for (i = 0; i < pll->rate_count; i++) { in rockchip_get_pll_settings()
67 struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw); in rockchip_pll_round_rate() local
68 const struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_pll_round_rate()
72 for (i = 0; i < pll->rate_count; i++) { in rockchip_pll_round_rate()
78 return rate_table[i - 1].rate; in rockchip_pll_round_rate()
[all …]
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| /linux-6.12.1/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 1 // SPDX-License-Identifier: GPL-2.0
18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
51 * CLK = ----------------------
68 * XCLK The clock rate of the on-chip memory
75 * SCLK Multi-purpose clock
77 * - MCLK and XCLK use the same FB_DIV
78 * - VCLK0 .. VCLK3 use the same FB_DIV
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| /linux-6.12.1/drivers/clk/samsung/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * This file contains the utility functions to register the pll clocks.
15 #include <linux/clk-provider.h>
18 #include "clk-pll.h"
27 /* PLL enable control bit offset in @con_reg register */
29 /* PLL lock status bit offset in @con_reg register */
39 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
41 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
44 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
55 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
[all …]
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| /linux-6.12.1/drivers/clk/visconti/ |
| D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti PLL driver
12 #include <linux/clk-provider.h>
17 #include "pll.h"
48 #define PLL_CREATE_FRACMODE(table) (table->dacen << 4 | table->dsmen)
49 #define PLL_CREATE_OSTDIV(table) (table->postdiv2 << 4 | table->postdiv1)
56 static void visconti_pll_get_params(struct visconti_pll *pll, in visconti_pll_get_params() argument
61 val = readl(pll->pll_base + PLL_FRACMODE_REG); in visconti_pll_get_params()
63 rate_table->dacen = FIELD_GET(PLL0_FRACMODE_DACEN, val); in visconti_pll_get_params()
64 rate_table->dsmen = FIELD_GET(PLL0_FRACMODE_DSMEN, val); in visconti_pll_get_params()
[all …]
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| /linux-6.12.1/drivers/clk/at91/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
20 #define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
21 (layout)->mul_mask)
23 #define PLL_MUL_MASK(layout) ((layout)->mul_mask)
57 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_prepare() local
58 struct regmap *regmap = pll->regmap; in clk_pll_prepare()
59 const struct clk_pll_layout *layout = pll->layout; in clk_pll_prepare()
61 pll->characteristics; in clk_pll_prepare()
62 u8 id = pll->id; in clk_pll_prepare()
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| /linux-6.12.1/drivers/clk/sophgo/ |
| D | clk-cv18xx-pll.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
11 #include "clk-cv18xx-pll.h"
36 struct cv1800_clk_pll *pll = hw_to_cv1800_clk_pll(hw); in ipll_recalc_rate() local
39 value = readl(pll->common.base + pll->pll_reg); in ipll_recalc_rate()
58 for_each_pll_limit_range(pre, &limit->pre_div) { in ipll_find_rate()
59 for_each_pll_limit_range(div, &limit->div) { in ipll_find_rate()
60 for_each_pll_limit_range(post, &limit->post_div) { in ipll_find_rate()
66 if ((trate - tmp) < (trate - best_rate)) { in ipll_find_rate()
85 return -EINVAL; in ipll_find_rate()
[all …]
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| /linux-6.12.1/drivers/clk/pistachio/ |
| D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
65 /* Fractional PLL operating modes */
78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
80 return readl(pll->base + reg); in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
85 writel(val, pll->base + reg); in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
107 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
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| /linux-6.12.1/drivers/clk/baikal-t1/ |
| D | ccu-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
20 #include <linux/clk-provider.h>
29 #include "ccu-pll.h"
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
107 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_enable() local
114 return -EINVAL; in ccu_pll_enable()
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| /linux-6.12.1/arch/mips/ath79/ |
| D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
17 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/ath79-clk.h>
24 #include <asm/mach-ath79/ath79.h>
25 #include <asm/mach-ath79/ar71xx_regs.h>
99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
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| /linux-6.12.1/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_phy_8996.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
33 /* pll mmio base */
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
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