| /linux-6.12.1/drivers/irqchip/ |
| D | irq-mvebu-pic.c | 36 static void mvebu_pic_reset(struct mvebu_pic *pic) in mvebu_pic_reset() argument
39 writel(0, pic->base + PIC_MASK); in mvebu_pic_reset()
40 writel(PIC_MAX_IRQ_MASK, pic->base + PIC_CAUSE); in mvebu_pic_reset()
45 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_eoi_irq() local
47 writel(1 << d->hwirq, pic->base + PIC_CAUSE); in mvebu_pic_eoi_irq()
52 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_mask_irq() local
55 reg = readl(pic->base + PIC_MASK); in mvebu_pic_mask_irq()
57 writel(reg, pic->base + PIC_MASK); in mvebu_pic_mask_irq()
62 struct mvebu_pic *pic = irq_data_get_irq_chip_data(d); in mvebu_pic_unmask_irq() local
65 reg = readl(pic->base + PIC_MASK); in mvebu_pic_unmask_irq()
[all …]
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| D | irq-or1k-pic.c | 13 /* OR1K PIC implementation */
48 * There are two oddities with the OR1200 PIC implementation:
66 .name = "or1k-PIC-level",
76 .name = "or1k-PIC-edge",
88 .name = "or1200-PIC",
123 struct or1k_pic_dev *pic = d->host_data; in or1k_map() local
125 irq_set_chip_and_handler(irq, &pic->chip, pic->handle); in or1k_map()
126 irq_set_status_flags(irq, pic->flags); in or1k_map()
137 * This sets up the IRQ domain for the PIC built in to the OpenRISC
142 struct or1k_pic_dev *pic) in or1k_pic_init() argument
[all …]
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| /linux-6.12.1/arch/mips/boot/dts/loongson/ |
| D | ls7a-pch.dtsi | 13 pic: interrupt-controller@10000000 { label
14 compatible = "loongson,pch-pic-1.0";
18 loongson,pic-base-vec = <0>;
25 interrupt-parent = <&pic>;
33 interrupt-parent = <&pic>;
43 interrupt-parent = <&pic>;
53 interrupt-parent = <&pic>;
63 interrupt-parent = <&pic>;
90 interrupt-parent = <&pic>;
101 interrupt-parent = <&pic>;
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | open-pic.txt | 1 * Open PIC Binding
4 representation of an Open PIC compliant interrupt controller. This binding is
5 based on the binding defined for Open PIC in [1] and is a superset of that
13 - compatible: Specifies the compatibility list for the PIC. The type
14 shall be <string> and the value shall include "open-pic".
17 PIC's addressable register space. The type shall be <prop-encoded-array>.
20 as an Open PIC. No property value shall be defined.
31 - pic-no-reset: The presence of this property indicates that the PIC
55 * An Open PIC interrupt controller
57 mpic: pic@40000 {
[all …]
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| D | loongson,pch-pic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
7 title: Loongson PCH PIC Controller
19 const: loongson,pch-pic-1.0
24 loongson,pic-base-vec:
27 to PCH PIC.
40 - loongson,pic-base-vec
49 pic: interrupt-controller@10000000 {
50 compatible = "loongson,pch-pic-1.0";
54 loongson,pic-base-vec = <64>;
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| D | opencores,or1k-pic.txt | 5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
20 compatible = "opencores,or1k-pic-level";
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| D | marvell,armada-8k-pic.txt | 1 Marvell Armada 7K/8K PIC Interrupt controller
4 This is the Device Tree binding for the PIC, a secondary interrupt
9 - compatible: should be "marvell,armada-8k-pic"
13 - reg: the register area for the PIC interrupt controller
19 pic: interrupt-controller@3f0100 {
20 compatible = "marvell,armada-8k-pic";
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| /linux-6.12.1/arch/powerpc/platforms/cell/ |
| D | spider-pic.c | 64 static void __iomem *spider_get_irq_config(struct spider_pic *pic, in spider_get_irq_config() argument
67 return pic->regs + TIR_CFGA + 8 * src; in spider_get_irq_config()
72 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_unmask_irq() local
73 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_unmask_irq()
80 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_mask_irq() local
81 void __iomem *cfg = spider_get_irq_config(pic, irqd_to_hwirq(d)); in spider_mask_irq()
88 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_ack_irq() local
101 out_be32(pic->regs + TIR_EDC, 0x100 | (src & 0xf)); in spider_ack_irq()
107 struct spider_pic *pic = spider_irq_data_to_pic(d); in spider_set_irq_type() local
109 void __iomem *cfg = spider_get_irq_config(pic, hw); in spider_set_irq_type()
[all …]
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| /linux-6.12.1/drivers/media/platform/verisilicon/ |
| D | hantro_g1_mpeg2_dec.c | 96 const struct v4l2_ctrl_mpeg2_picture *pic) in hantro_g1_mpeg2_dec_set_buffers() argument
101 switch (pic->picture_coding_type) { in hantro_g1_mpeg2_dec_set_buffers()
103 backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts); in hantro_g1_mpeg2_dec_set_buffers()
106 forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts); in hantro_g1_mpeg2_dec_set_buffers()
117 if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) in hantro_g1_mpeg2_dec_set_buffers()
127 if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME || in hantro_g1_mpeg2_dec_set_buffers()
128 pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B || in hantro_g1_mpeg2_dec_set_buffers()
129 (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD && in hantro_g1_mpeg2_dec_set_buffers()
130 pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST) || in hantro_g1_mpeg2_dec_set_buffers()
131 (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD && in hantro_g1_mpeg2_dec_set_buffers()
[all …]
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| D | rockchip_vpu2_hw_mpeg2_dec.c | 99 const struct v4l2_ctrl_mpeg2_picture *pic) in rockchip_vpu2_mpeg2_dec_set_buffers() argument
104 switch (pic->picture_coding_type) { in rockchip_vpu2_mpeg2_dec_set_buffers()
106 backward_addr = hantro_get_ref(ctx, pic->backward_ref_ts); in rockchip_vpu2_mpeg2_dec_set_buffers()
109 forward_addr = hantro_get_ref(ctx, pic->forward_ref_ts); in rockchip_vpu2_mpeg2_dec_set_buffers()
120 if (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD) in rockchip_vpu2_mpeg2_dec_set_buffers()
130 if (pic->picture_structure == V4L2_MPEG2_PIC_FRAME || in rockchip_vpu2_mpeg2_dec_set_buffers()
131 pic->picture_coding_type == V4L2_MPEG2_PIC_CODING_TYPE_B || in rockchip_vpu2_mpeg2_dec_set_buffers()
132 (pic->picture_structure == V4L2_MPEG2_PIC_TOP_FIELD && in rockchip_vpu2_mpeg2_dec_set_buffers()
133 pic->flags & V4L2_MPEG2_PIC_TOP_FIELD) || in rockchip_vpu2_mpeg2_dec_set_buffers()
134 (pic->picture_structure == V4L2_MPEG2_PIC_BOTTOM_FIELD && in rockchip_vpu2_mpeg2_dec_set_buffers()
[all …]
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| /linux-6.12.1/arch/m68k/virt/ |
| D | ints.c | 34 * 6 goldfish-pic for CPU IRQ #1 to IRQ #6
35 * CPU IRQ #1 -> PIC #1
38 * CPU IRQ #2 -> PIC #2
40 * CPU IRQ #3 -> PIC #3
42 * CPU IRQ #4 -> PIC #4
44 * CPU IRQ #5 -> PIC #5
46 * CPU IRQ #6 -> PIC #6
53 static u32 gfpic_read(int pic, int reg) in gfpic_read() argument
55 void __iomem *base = (void __iomem *)(virt_bi_data.pic.mmio + in gfpic_read()
56 pic * 0x1000); in gfpic_read()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | v3-v360epc-pci.txt | 39 interrupt-parent = <&pic>;
56 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
57 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
58 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
59 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
61 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
62 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
63 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
64 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
66 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
[all …]
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| /linux-6.12.1/arch/loongarch/boot/dts/ |
| D | loongson-2k2000.dtsi | 148 pic: interrupt-controller@10000000 { label
149 compatible = "loongson,pch-pic-1.0";
153 loongson,pic-base-vec = <0>;
171 interrupt-parent = <&pic>;
203 interrupt-parent = <&pic>;
212 interrupt-parent = <&pic>;
221 interrupt-parent = <&pic>;
228 interrupt-parent = <&pic>;
235 interrupt-parent = <&pic>;
242 interrupt-parent = <&pic>;
[all …]
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| /linux-6.12.1/drivers/staging/media/sunxi/cedrus/ |
| D | cedrus_mpeg2.c | 54 const struct v4l2_ctrl_mpeg2_picture *pic; in cedrus_mpeg2_setup() local
64 pic = run->mpeg2.picture; in cedrus_mpeg2_setup()
91 reg = VE_DEC_MPEG_MP12HDR_SLICE_TYPE(pic->picture_coding_type); in cedrus_mpeg2_setup()
92 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 0, pic->f_code[0][0]); in cedrus_mpeg2_setup()
93 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(0, 1, pic->f_code[0][1]); in cedrus_mpeg2_setup()
94 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 0, pic->f_code[1][0]); in cedrus_mpeg2_setup()
95 reg |= VE_DEC_MPEG_MP12HDR_F_CODE(1, 1, pic->f_code[1][1]); in cedrus_mpeg2_setup()
96 reg |= VE_DEC_MPEG_MP12HDR_INTRA_DC_PRECISION(pic->intra_dc_precision); in cedrus_mpeg2_setup()
97 reg |= VE_DEC_MPEG_MP12HDR_INTRA_PICTURE_STRUCTURE(pic->picture_structure); in cedrus_mpeg2_setup()
98 reg |= VE_DEC_MPEG_MP12HDR_TOP_FIELD_FIRST(pic->flags & V4L2_MPEG2_PIC_FLAG_TOP_FIELD_FIRST); in cedrus_mpeg2_setup()
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/arm/ |
| D | integratorap.dts | 149 pic: pic@14000000 { label
161 interrupt-parent = <&pic>;
178 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
179 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
180 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
181 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
183 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
184 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
185 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
186 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
[all …]
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| /linux-6.12.1/arch/xtensa/boot/dts/ |
| D | virt.dts | 8 interrupt-parent = <&pic>;
37 pic: pic { label
38 compatible = "cdns,xtensa-pic";
64 0x0000 0x0 0x0 0x1 &pic 0x0 0x1
65 0x0800 0x0 0x0 0x1 &pic 0x1 0x1
66 0x1000 0x0 0x0 0x1 &pic 0x2 0x1
67 0x1800 0x0 0x0 0x1 &pic 0x3 0x1
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| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | tqm8xx.dts | 39 interrupt-parent = <&PIC>;
73 interrupt-parent = <&PIC>;
85 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: pic@0 { label
124 compatible = "fsl,mpc860-pic", "fsl,pq1-pic";
156 CPM_PIC: pic@930 {
161 interrupt-parent = <&PIC>;
163 compatible = "fsl,mpc860-cpm-pic",
164 "fsl,cpm1-pic";
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| D | ep8248e.dts | 72 interrupt-parent = <&PIC>;
77 interrupt-parent = <&PIC>;
135 interrupt-parent = <&PIC>;
148 interrupt-parent = <&PIC>;
161 interrupt-parent = <&PIC>;
174 interrupt-parent = <&PIC>;
186 interrupt-parent = <&PIC>;
192 PIC: interrupt-controller@10c00 { label
196 compatible = "fsl,mpc8248-pic", "fsl,pq2-pic";
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| D | mpc866ads.dts | 32 interrupt-parent = <&PIC>;
83 interrupt-parent = <&PIC>;
88 PIC: pic@0 { label
92 compatible = "fsl,mpc866-pic", "fsl,pq1-pic";
124 CPM_PIC: pic@930 {
129 interrupt-parent = <&PIC>;
131 compatible = "fsl,mpc866-cpm-pic",
132 "fsl,cpm1-pic";
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| D | mpc885ads.dts | 32 interrupt-parent = <&PIC>;
103 interrupt-parent = <&PIC>;
115 interrupt-parent = <&PIC>;
120 PIC: interrupt-controller@0 { label
124 compatible = "fsl,mpc885-pic", "fsl,pq1-pic";
134 interrupt-parent = <&PIC>;
171 interrupt-parent = <&PIC>;
173 compatible = "fsl,mpc885-cpm-pic",
174 "fsl,cpm1-pic";
228 interrupt-parent = <&PIC>;
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| /linux-6.12.1/arch/powerpc/platforms/52xx/ |
| D | lite5200_pm.c | 15 static struct mpc52xx_intr __iomem *pic; variable
78 pic = mbar + 0x500; in lite5200_pm_prepare()
100 _memcpy_fromio(&spic, pic, sizeof(*pic)); in lite5200_save_regs()
188 /* PIC */ in lite5200_restore_regs()
189 out_be32(&pic->per_pri1, spic.per_pri1); in lite5200_restore_regs()
190 out_be32(&pic->per_pri2, spic.per_pri2); in lite5200_restore_regs()
191 out_be32(&pic->per_pri3, spic.per_pri3); in lite5200_restore_regs()
193 out_be32(&pic->main_pri1, spic.main_pri1); in lite5200_restore_regs()
194 out_be32(&pic->main_pri2, spic.main_pri2); in lite5200_restore_regs()
196 out_be32(&pic->enc_status, spic.enc_status); in lite5200_restore_regs()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/ |
| D | pic.txt | 4 - fsl,cpm1-pic
6 - fsl,pq1-pic
7 - fsl,cpm2-pic
17 compatible = "mpc8272-pic", "fsl,cpm2-pic";
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| /linux-6.12.1/arch/sparc/include/uapi/asm/ |
| D | perfctr.h | 26 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
38 /* Add current D0 and D1 PIC values into user pointers given
39 * in PERFCTR_ON operation. The PIC is cleared before returning.
43 /* Clear the PIC register. */
47 * in ARG0. The PIC is also cleared after the new PCR value is
62 /* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
76 /* Pic.S0 Selection Bit Field Encoding, Ultra-III */
107 /* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
121 /* Pic.S1 Selection Bit Field Encoding, Ultra-III */
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| /linux-6.12.1/arch/alpha/kernel/ |
| D | irq_i8259.c | 76 .name = "XT-PIC",
120 * Generate a PCI interrupt acknowledge cycle. The PIC will in isa_device_interrupt()
135 unsigned long pic; in isa_no_iack_sc_device_interrupt() local
150 pic = inb(0x20) | (inb(0xA0) << 8); /* read isr */ in isa_no_iack_sc_device_interrupt()
151 pic &= 0xFFFB; /* mask out cascade & hibits */ in isa_no_iack_sc_device_interrupt()
153 while (pic) { in isa_no_iack_sc_device_interrupt()
154 int j = ffz(~pic); in isa_no_iack_sc_device_interrupt()
155 pic &= pic - 1; in isa_no_iack_sc_device_interrupt()
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| /linux-6.12.1/drivers/gpio/ |
| D | gpio-idt3243x.c | 22 void __iomem *pic; member
37 pending = readl(ctrl->pic + IDT_PIC_IRQ_PEND); in idt_gpio_dispatch()
92 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); in idt_gpio_mask()
109 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); in idt_gpio_unmask()
120 writel(ctrl->mask_cache, ctrl->pic + IDT_PIC_IRQ_MASK); in idt_gpio_irq_init_hw()
167 ctrl->pic = devm_platform_ioremap_resource_byname(pdev, "pic"); in idt_gpio_probe()
168 if (IS_ERR(ctrl->pic)) in idt_gpio_probe()
169 return PTR_ERR(ctrl->pic); in idt_gpio_probe()
209 MODULE_DESCRIPTION("IDT 79RC3243x GPIO/PIC Driver");
|