| /linux-6.12.1/arch/arm/mach-s3c/ |
| D | setup-usb-phy-s3c64xx.c | 26 u32 phyclk; in s3c_usb_otgphy_init() local
31 phyclk = readl(S3C_PHYCLK) & ~S3C_PHYCLK_CLKSEL_MASK; in s3c_usb_otgphy_init()
37 phyclk |= S3C_PHYCLK_CLKSEL_12M; in s3c_usb_otgphy_init()
40 phyclk |= S3C_PHYCLK_CLKSEL_24M; in s3c_usb_otgphy_init()
51 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init()
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| /linux-6.12.1/drivers/phy/samsung/ |
| D | phy-exynos5250-sata.c | 50 struct clk *phyclk; member
196 sata_phy->phyclk = devm_clk_get(dev, "sata_phyctrl"); in exynos_sata_phy_probe()
197 if (IS_ERR(sata_phy->phyclk)) { in exynos_sata_phy_probe()
199 ret = PTR_ERR(sata_phy->phyclk); in exynos_sata_phy_probe()
203 ret = clk_prepare_enable(sata_phy->phyclk); in exynos_sata_phy_probe()
228 clk_disable_unprepare(sata_phy->phyclk); in exynos_sata_phy_probe()
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| /linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwmac-stm32.c | 76 *| | | st,ext-phyclk | | |
79 *| | | st,ext-phyclk | | |
82 *| | | st,ext-phyclk | | st,eth-clk-sel or|
83 *| | | | | st,ext-phyclk |
86 *| | | st,ext-phyclk | st,eth-ref-clk-sel | |
87 *| | | | or st,ext-phyclk | |
457 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); in stm32mp1_parse_data()
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| D | dwmac-sti.c | 55 *| | |clkgen/phyclk-in |
66 * phyclk| 1 | 0 | n/a |
228 dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); in sti_dwmac_parse_data()
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | rockchip,inno-usb2phy.yaml | 40 const: phyclk
186 clock-names = "phyclk";
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| D | rockchip-usb-phy.yaml | 47 const: phyclk
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_mcg/ |
| D | dml2_mcg_dcn4.c | 183 …min_table->max_clocks_khz.phyclk = soc_bb->clk_table.phyclk.clk_values_khz[soc_bb->clk_table.phycl… in build_min_clock_table()
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| /linux-6.12.1/drivers/net/wireless/ath/ath10k/ |
| D | hw.c | 601 u32 phyclk; in ath10k_hw_qca988x_set_coverage_class() local
626 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; in ath10k_hw_qca988x_set_coverage_class()
652 if (slottime_reg % phyclk) { in ath10k_hw_qca988x_set_coverage_class()
660 slottime = slottime / phyclk; in ath10k_hw_qca988x_set_coverage_class()
674 slottime += value * 3 * phyclk; in ath10k_hw_qca988x_set_coverage_class()
681 ack_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
687 cts_timeout += 3 * value * phyclk; in ath10k_hw_qca988x_set_coverage_class()
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| /linux-6.12.1/drivers/phy/freescale/ |
| D | phy-fsl-samsung-hdmi.c | 582 struct clk *phyclk; in phy_clk_register() local
595 phyclk = devm_clk_register(dev, &phy->hw); in phy_clk_register()
596 if (IS_ERR(phyclk)) in phy_clk_register()
597 return dev_err_probe(dev, PTR_ERR(phyclk), in phy_clk_register()
600 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk); in phy_clk_register()
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | sti-dwmac.txt | 20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
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| D | stm32-dwmac.yaml | 92 st,ext-phyclk:
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| /linux-6.12.1/Documentation/devicetree/bindings/usb/ |
| D | samsung,exynos-dwc3.yaml | 104 - const: phyclk
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| D | dml_top_soc_parameter_types.h | 122 struct dml2_clk_table phyclk; member
|
| /linux-6.12.1/arch/arm/boot/dts/st/ |
| D | stm32mp135f-dhcor-dhsbc.dts | 85 st,ext-phyclk;
134 st,ext-phyclk;
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| D | stih407-pinctrl.dtsi | 218 phyclk = <&pio2 3 ALT4 OUT NICLK 1250 CLK_B>;
260 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
281 phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
287 phyclk = <&pio2 3 ALT2 IN NICLK 0 CLK_A>;
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| /linux-6.12.1/drivers/phy/rockchip/ |
| D | phy-rockchip-inno-hdmi.c | 245 struct clk *phyclk; member
638 ret = clk_prepare_enable(inno->phyclk); in inno_hdmi_phy_power_on()
644 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_on()
660 clk_disable_unprepare(inno->phyclk); in inno_hdmi_phy_power_off()
1017 inno->phyclk = devm_clk_register(dev, &inno->hw); in inno_hdmi_phy_clk_register()
1018 if (IS_ERR(inno->phyclk)) { in inno_hdmi_phy_clk_register()
1019 ret = PTR_ERR(inno->phyclk); in inno_hdmi_phy_clk_register()
1024 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk); in inno_hdmi_phy_clk_register()
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| /linux-6.12.1/drivers/clk/st/ |
| D | clk-flexgen.c | 360 { .name = "clk-eth-ref-phyclk", },
405 { .name = "clk-eth-ref-phyclk", },
460 { .name = "clk-eth-ref-phyclk", },
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| /linux-6.12.1/drivers/usb/dwc3/ |
| D | dwc3-exynos.c | 155 .clk_names = { "aclk", "susp_clk", "pipe_pclk", "phyclk" },
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/st/ |
| D | st,flexgen.txt | 128 "clk-eth-ref-phyclk",
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/ |
| D | dcn4_soc_bb.h | 110 .phyclk = {
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| D | dcn3_soc_bb.h | 160 .phyclk = {
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 158 /* PHYCLK */ in dcn3_init_clocks()
464 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 333 clock-names = "phyclk";
|
| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 300 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
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| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rk3066a.dtsi | 715 clock-names = "phyclk";
723 clock-names = "phyclk";
|