| /linux-6.12.1/Documentation/devicetree/bindings/usb/ |
| D | amlogic,meson-g12a-usb-ctrl.yaml | 114 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
133 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
153 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
168 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
187 - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used
214 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
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| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-388-clearfog-base.dts | 33 phy = <&phy1>;
41 line-name = "phy1-reset";
47 phy1: ethernet-phy@1 { label
59 /* phy1 reset */
|
| /linux-6.12.1/drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 257 struct iss_csiphy *phy1 = &iss->csiphy1; in omap4iss_csiphy_init() local
260 phy1->iss = iss; in omap4iss_csiphy_init()
261 phy1->csi2 = &iss->csi2a; in omap4iss_csiphy_init()
262 phy1->max_data_lanes = ISS_CSIPHY1_NUM_DATA_LANES; in omap4iss_csiphy_init()
263 phy1->used_data_lanes = 0; in omap4iss_csiphy_init()
264 phy1->cfg_regs = OMAP4_ISS_MEM_CSI2_A_REGS1; in omap4iss_csiphy_init()
265 phy1->phy_regs = OMAP4_ISS_MEM_CAMERARX_CORE1; in omap4iss_csiphy_init()
266 mutex_init(&phy1->mutex); in omap4iss_csiphy_init()
|
| /linux-6.12.1/Documentation/firmware-guide/acpi/dsd/ |
| D | phy.rst | 34 Device(PHY1) {
36 } // end of PHY1
46 as device object references (e.g. \_SB.MDI0.PHY1).
99 The PHY1 and PHY2 nodes represent the PHYs connected to MDIO bus MDI0
106 Device(PHY1) {
108 } // end of PHY1
130 Package (2) {"phy-handle", \_SB.MDI0.PHY1}
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | qcom,sm8450-dispcc.yaml | 32 - description: Byte clock from DSI PHY1
33 - description: Pixel clock from DSI PHY1
36 - description: Link clock from DP PHY1
37 - description: VCO DIV clock from DP PHY1
|
| D | qcom,sm8550-dispcc.yaml | 37 - description: Byte clock from DSI PHY1
38 - description: Pixel clock from DSI PHY1
41 - description: Link clock from DP PHY1
42 - description: VCO DIV clock from DP PHY1
|
| D | qcom,gcc-msm8953.yaml | 29 - description: Byte clock from DSI PHY1
30 - description: Pixel clock from DSI PHY1
|
| /linux-6.12.1/drivers/media/platform/ti/omap3isp/ |
| D | ispcsiphy.c | 75 /* Only the CCP2B on PHY1 is configurable. */ in csiphy_routing_cfg_3430()
338 struct isp_csiphy *phy1 = &isp->isp_csiphy1; in omap3isp_csiphy_init() local
348 phy1->isp = isp; in omap3isp_csiphy_init()
349 mutex_init(&phy1->mutex); in omap3isp_csiphy_init()
352 phy1->csi2 = &isp->isp_csi2c; in omap3isp_csiphy_init()
353 phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES; in omap3isp_csiphy_init()
354 phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1; in omap3isp_csiphy_init()
355 phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1; in omap3isp_csiphy_init()
|
| /linux-6.12.1/arch/arm/boot/dts/renesas/ |
| D | r8a7743-sk-rzg1m.dts | 51 phy1_pins: phy1 {
68 phy-handle = <&phy1>;
72 phy1: ethernet-phy@1 { label
|
| D | r8a7745-sk-rzg1e.dts | 46 phy1_pins: phy1 {
63 phy-handle = <&phy1>;
67 phy1: ethernet-phy@1 { label
|
| /linux-6.12.1/arch/riscv/boot/dts/starfive/ |
| D | jh7110-pine64-star64.dts | 24 phy-handle = <&phy1>;
36 phy1: ethernet-phy@1 { label
56 &phy1 {
|
| D | jh7110-starfive-visionfive-2.dtsi | 17 phy-handle = <&phy1>;
26 phy1: ethernet-phy@1 { label
|
| /linux-6.12.1/arch/arm64/boot/dts/broadcom/stingray/ |
| D | stingray-usb.dtsi | 29 phy-names = "phy0", "phy1";
39 phy-names = "phy0", "phy1";
63 phy-names = "phy0", "phy1", "phy2";
|
| /linux-6.12.1/drivers/gpio/ |
| D | gpio-stp-xway.c | 87 u8 phy1; /* 3 bits can be driven by phy1 */ member
193 chip->phy1 << XWAY_STP_PHY1_SHIFT, in xway_stp_hw_init()
217 | (chip->phy1 << 2) | chip->dsl; in xway_stp_hw_init()
278 if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy)) in xway_stp_probe()
279 chip->phy1 = phy & XWAY_STP_PHY_MASK; in xway_stp_probe()
|
| /linux-6.12.1/drivers/staging/media/max96712/ |
| D | max96712.c | 133 /* Configure a 3-lane C-PHY using PHY0 and PHY1. */ in max96712_mipi_configure()
140 /* Configure a 4-lane D-PHY using PHY0 and PHY1. */ in max96712_mipi_configure()
144 /* Configure lane mapping for PHY0 and PHY1. */ in max96712_mipi_configure()
148 /* Configure lane polarity for PHY0 and PHY1. */ in max96712_mipi_configure()
154 /* Set link frequency for PHY0 and PHY1. */ in max96712_mipi_configure()
160 /* Enable PHY0 and PHY1 */ in max96712_mipi_configure()
|
| /linux-6.12.1/arch/arm/boot/dts/axis/ |
| D | artpec6-devboard.dts | 51 phy-handle = <&phy1>;
58 phy1: phy@0 { label
|
| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1028a-kontron-sl28-var4.dts | 22 phy1: ethernet-phy@4 { label
44 phy-handle = <&phy1>;
|
| D | fsl-ls1028a-kontron-sl28-var2.dts | 21 phy1: ethernet-phy@4 { label
67 phy-handle = <&phy1>;
|
| /linux-6.12.1/arch/arm/boot/dts/allwinner/ |
| D | sun7i-a20-icnova-a20.dtsi | 16 phy-handle = <&phy1>;
32 phy1: ethernet-phy@1 { label
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | socionext,synquacer-netsec.yaml | 62 phy-handle = <&phy1>;
67 phy1: ethernet-phy@1 {
|
| /linux-6.12.1/arch/riscv/boot/dts/microchip/ |
| D | mpfs-polarberry.dts | 45 phy-handle = <&phy1>;
48 phy1: ethernet-phy@5 { label
|
| /linux-6.12.1/arch/arm/boot/dts/intel/ixp/ |
| D | intel-ixp42x-ixdp425.dts | 57 phy1: ethernet-phy@1 { label
69 phy-handle = <&phy1>;
|
| D | intel-ixp43x-kixrp435.dts | 43 phy-handle = <&phy1>;
49 phy1: ethernet-phy@1 { label
|
| /linux-6.12.1/arch/arm/boot/dts/hisilicon/ |
| D | hisi-x5hd2-dkb.dts | 69 phy-handle = <&phy1>;
75 phy1: ethernet-phy@1 { label
|
| /linux-6.12.1/arch/loongarch/boot/dts/ |
| D | loongson-2k2000-ref.dts | 81 phy-handle = <&phy1>;
86 phy1: ethernet-phy@1 { label
|