Searched +full:phy +full:- +full:is +full:- +full:integrated (Results 1 – 25 of 121) sorted by relevance
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/linux-6.12.1/Documentation/networking/dsa/ |
D | bcm_sf2.rst | 5 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and 8 - xDSL gateways such as BCM63138 9 - streaming/multimedia Set Top Box such as BCM7445 10 - Cable Modem/residential gateways such as BCM7145/BCM3390 12 The switch is typically deployed in a configuration involving between 5 to 13 13 ports, offering a range of built-in and customizable interfaces: 15 - single integrated Gigabit PHY 16 - quad integrated Gigabit PHY 17 - quad external Gigabit PHY w/ MDIO multiplexer 18 - integrated MoCA PHY [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Ethernet PHY Common Properties 10 - Andrew Lunn <andrew@lunn.ch> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Heiner Kallweit <hkallweit1@gmail.com> 14 # The dt-schema tools will generate a select statement first by using 16 # case, the node name is the one we want to match on, while the [all …]
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D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Horatiu Vultur <horatiu.vultur@microchip.com> 13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with 14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs, 15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to 16 2 Quad-SGMII/Quad-USGMII interfaces. 20 pattern: "^switch@[0-9a-f]+$" [all …]
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D | snps,dwc-qos-ethernet.txt | 3 This binding is deprecated, but it continues to be supported, but new 13 - compatible: One of: 14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10" 15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC. 16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10" 17 Represents the IP core when integrated into the NVIDIA Tegra186 SoC. 18 - "snps,dwc-qos-ethernet-4.10" 19 This combination is deprecated. It should be treated as equivalent to 20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be 22 - reg: Address and length of the register set for the device [all …]
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D | allwinner,sun8i-a83t-emac.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 16 - const: allwinner,sun8i-a83t-emac 17 - const: allwinner,sun8i-h3-emac 18 - const: allwinner,sun8i-r40-gmac 19 - const: allwinner,sun8i-v3s-emac [all …]
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D | adi,adin1110.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ADI ADIN1110 MAC-PHY 10 - Alexandru Tachici <alexandru.tachici@analog.com> 13 The ADIN1110 is a low power single port 10BASE-T1L MAC- 14 PHY designed for industrial Ethernet applications. It integrates 15 an Ethernet PHY core with a MAC and all the associated analog 18 The ADIN2111 is a low power, low complexity, two-Ethernet ports 19 switch with integrated 10BASE-T1L PHYs and one serial peripheral [all …]
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D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI DP83869 ethernet PHY 11 - $ref: ethernet-phy.yaml# 14 - Andrew Davis <afd@ti.com> 17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver 18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and 19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and 20 100BASE-FX Fiber protocols. [all …]
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D | cortina,gemini-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 13 This ethernet controller is found in the Gemini SoC family: 19 const: cortina,gemini-ethernet 23 description: must contain the global registers and the V-bit and A-bit 26 "#address-cells": 29 "#size-cells": [all …]
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D | microchip,lan8650.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers 10 - Parthiban Veerasooran <parthiban.veerasooran@microchip.com> 14 PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller 16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver 17 integrated into the LAN8650/1. The communication between the Host and 18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial 22 - $ref: /schemas/net/ethernet-controller.yaml# [all …]
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D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: TI DP83867 ethernet PHY 11 - $ref: ethernet-controller.yaml# 14 - Andrew Davis <afd@ti.com> 17 The DP83867 device is a robust, low power, fully featured Physical Layer 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. 21 The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet [all …]
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D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - David S. Miller <davem@davemloft.net> 19 local-mac-address: 22 $ref: /schemas/types.yaml#/definitions/uint8-array 26 mac-address: 30 to the device by the boot program is different from the 31 local-mac-address property. [all …]
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D | brcm,unimac-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/net/brcm,unimac-mdio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Doug Berger <opendmb@gmail.com> 11 - Florian Fainelli <f.fainelli@gmail.com> 12 - Rafał Miłecki <rafal@milecki.pl> 15 - $ref: mdio.yaml# 20 - brcm,genet-mdio-v1 21 - brcm,genet-mdio-v2 [all …]
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/linux-6.12.1/drivers/net/phy/ |
D | intel-xway.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de> 9 #include <linux/phy.h> 22 #define XWAY_MDIO_LED_LED3_EN BIT(11) /* Enable the integrated function of LED3 */ 23 #define XWAY_MDIO_LED_LED2_EN BIT(10) /* Enable the integrated function of LED2 */ 24 #define XWAY_MDIO_LED_LED1_EN BIT(9) /* Enable the integrated function of LED1 */ 25 #define XWAY_MDIO_LED_LED0_EN BIT(8) /* Enable the integrated function of LED0 */ 32 #define XWAY_MDIO_INIT_WOL BIT(15) /* Wake-On-LAN */ 36 #define XWAY_MDIO_INIT_ANE BIT(11) /* Auto-Neg error */ 37 #define XWAY_MDIO_INIT_ANC BIT(10) /* Auto-Neg complete */ [all …]
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D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # PHY Layer Configuration 12 PHYlink models the link between the PHY and MAC, allowing fixed 17 tristate "PHY Device support and infrastructure" 22 Ethernet controllers are usually attached to PHY 24 managing PHY devices. 35 Adds support for a set of LED trigger events per-PHY. Link 38 supported by the PHY and also a one common "link" trigger as a 39 logical-or of all the link speed ones. 41 <mii bus id>:<phy>:<speed> [all …]
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D | bcm63xx.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Driver for Broadcom 63xx SOCs integrated PHYs 5 #include "bcm-phy-lib.h" 7 #include <linux/phy.h> 16 MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver"); 28 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in bcm63xx_config_intr() 51 /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */ in bcm63xx_config_init() 52 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported); in bcm63xx_config_init() 83 /* same phy as above, with just a different OUI */
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/linux-6.12.1/Documentation/devicetree/bindings/net/dsa/ |
D | vitesse,vsc73xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 13 The Vitesse DSA Switches were produced in the early-to-mid 2000s. 19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch 20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch 21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch 22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch 26 If SPI interface is used, the device tree node is an SPI device so it must [all …]
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D | renesas,rzn1-a5psw.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Clément Léger <clement.leger@bootlin.com> 13 The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and 17 - $ref: dsa.yaml#/$defs/ethernet-ports 22 - enum: 23 - renesas,r9a06g032-a5psw 24 - const: renesas,rzn1-a5psw [all …]
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D | mscc,ocelot.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Vladimir Oltean <vladimir.oltean@nxp.com> 11 - Claudiu Manoil <claudiu.manoil@nxp.com> 12 - Alexandre Belloni <alexandre.belloni@bootlin.com> 13 - UNGLinuxDriver@microchip.com 16 There are multiple switches which are either part of the Ocelot-1 family, or 21 (which is attached to an Ethernet port of the host), rather than through 22 Frame DMA or register-based I/O. [all …]
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D | lan9303.txt | 2 ------------------------------------------------- 6 - compatible: should be 7 - "smsc,lan9303-i2c" for I2C managed mode 9 - "smsc,lan9303-mdio" for mdio managed mode 13 - reset-gpios: GPIO to be used to reset the whole device 14 - reset-duration: reset duration in milliseconds, defaults to 200 ms 18 The integrated switch subnode should be specified according to the binding 19 described in dsa/dsa.txt. The CPU port of this switch is always port 0. 21 Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is 23 auto-detected and mapped accordingly. [all …]
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/linux-6.12.1/drivers/net/ethernet/wiznet/ |
D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 26 W5100 is a single chip with integrated 10/100 Ethernet MAC, 27 PHY and hardware TCP/IP stack, but this driver is limited to 28 the MAC and PHY functions only, onchip TCP/IP is unused. 39 W5300 is a single chip with integrated 10/100 Ethernet MAC, 40 PHY and hardware TCP/IP stack, but this driver is limited to 41 the MAC and PHY functions only, onchip TCP/IP is unused. 55 after mapping to Memory-Mapped I/O space. 62 which are directly mapped to Memory-Mapped I/O space. 67 If interface mode is unknown in compile time, it can be selected [all …]
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/linux-6.12.1/arch/arm/boot/dts/rockchip/ |
D | rk3228-evb.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 /dts-v1/; 9 compatible = "rockchip,rk3228-evb", "rockchip,rk3228"; 20 vcc_phy: vcc-phy-regulator { 21 compatible = "regulator-fixed"; 22 enable-active-high; 23 regulator-name = "vcc_phy"; 24 regulator-min-microvolt = <1800000>; 25 regulator-max-microvolt = <1800000>; 26 regulator-always-on; [all …]
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/linux-6.12.1/drivers/scsi/mpt3sas/ |
D | mpt3sas_base.h | 2 * This is the Fusion MPT base driver providing common API layer interface 5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.h 6 * Copyright (C) 2012-2014 LSI Corporation 7 * Copyright (C) 2013-2014 Avago Technologies 8 * (mailto: MPT-FusionLinux.pdl@avagotech.com) 10 * This program is free software; you can redistribute it and/or 15 * This program is distributed in the hope that it will be useful, 21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR 23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, 24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/usb/ |
D | iproc-udc.txt | 3 The device node is used for UDCs integrated into Broadcom's 4 iProc family (Northstar2, Cygnus) of SoCs'. The UDC is based 9 - compatible: Add the compatibility strings for supported platforms. 10 For Broadcom NS2 platform, add "brcm,ns2-udc","brcm,iproc-udc". 11 For Broadcom Cygnus platform, add "brcm,cygnus-udc", "brcm,iproc-udc". 12 - reg: Offset and length of UDC register set 13 - interrupts: description of interrupt line 14 - phys: phandle to phy node. 18 compatible = "brcm,ns2-udc", "brcm,iproc-udc";
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/linux-6.12.1/drivers/net/mdio/ |
D | mdio-bcm-unimac.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2014-2017 Broadcom 16 #include <linux/phy.h> 17 #include <linux/platform_data/mdio-bcm-unimac.h> 50 * peripheral registers for CPU-native byte order. in unimac_mdio_readl() 53 return __raw_readl(priv->base + offset); in unimac_mdio_readl() 55 return readl_relaxed(priv->base + offset); in unimac_mdio_readl() 62 __raw_writel(val, priv->base + offset); in unimac_mdio_writel() 64 writel_relaxed(val, priv->base + offset); in unimac_mdio_writel() 83 * if C45 support is added. in unimac_mdio_poll() [all …]
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/linux-6.12.1/arch/arc/boot/dts/ |
D | vdk_axs10x_mb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) 10 compatible = "simple-bus"; 11 #address-cells = <1>; 12 #size-cells = <1>; 14 interrupt-parent = <&mb_intc>; 18 compatible = "fixed-clock"; 19 clock-frequency = <50000000>; 20 #clock-cells = <0>; 24 compatible = "fixed-clock"; [all …]
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