| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | qcom,sc8280xp-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
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| D | hisilicon,phy-hi3670-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3670-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin970 PCIe PHY
10 - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
13 Bindings for PCIe PHY on HiSilicon Kirin 970.
17 const: hisilicon,hi970-pcie-phy
19 "#phy-cells":
24 description: PHY Control registers
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| D | brcm,cygnus-pcie-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,cygnus-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Cygnus PCIe PHY
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
15 pattern: "^pcie[-|_]phy(@.*)?$"
19 - const: brcm,cygnus-pcie-phy
24 Base address and length of the PCIe PHY block
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| D | lantiq,vrx200-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lantiq VRX200 and ARX300 PCIe PHY
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
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| D | airoha,en7581-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 PCI-Express PHY
10 - Lorenzo Bianconi <lorenzo@kernel.org>
13 The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
17 const: airoha,en7581-pcie-phy
21 - description: PCIE analog base address
22 - description: PCIE lane0 base address
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| D | qcom,ipq8074-qmp-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, IPQ8074)
10 - Vinod Koul <vkoul@kernel.org>
13 QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,ipq6018-qmp-pcie-phy
20 - qcom,ipq8074-qmp-gen3-pcie-phy
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| D | socionext,uniphier-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe PHY
10 This describes the devicetree bindings for PHY interface built into
11 PCIe controller implemented on Socionext UniPhier SoCs.
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - socionext,uniphier-pro5-pcie-phy
20 - socionext,uniphier-ld20-pcie-phy
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| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
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| D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8 SoC series PCIe PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
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| D | brcm,sr-pcie-phy.txt | 1 Broadcom Stingray PCIe PHY
4 - compatible: must be "brcm,sr-pcie-phy"
5 - reg: base address and length of the PCIe SS register space
6 - brcm,sr-cdru: phandle to the CDRU syscon node
7 - brcm,sr-mhb: phandle to the MHB syscon node
8 - #phy-cells: Must be 1, denotes the PHY index
11 PHY index goes from 0 to 7
13 For the internal PAXC based root complex, PHY index is always 8
17 compatible = "brcm,sr-mhb", "syscon";
22 compatible = "brcm,sr-cdru", "syscon";
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| /linux-6.12.1/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 1 // SPDX-License-Identifier: GPL-2.0
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
9 #include "pcie-cadence.h"
11 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
19 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
24 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
27 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
35 u64 sz = 1ULL << fls64(size - 1); in cdns_pcie_set_outbound_region()
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
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| /linux-6.12.1/drivers/pci/controller/dwc/ |
| D | pcie-armada8k.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Marvell Armada-8K SoCs
5 * Armada-8K PCIe Glue Layer Source Code
20 #include <linux/phy/phy.h>
25 #include "pcie-designware.h"
33 struct phy *phy[ARMADA8K_PCIE_MAX_LANES]; member
61 * AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
71 #define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
73 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
78 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
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| D | pcie-kirin.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Kirin Phone SoCs
20 #include <linux/phy/phy.h>
27 #include "pcie-designware.h"
29 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
31 /* PCIe ELBI registers */
58 * in-board Ethernet adapter and the other two connected to M.2 and mini
75 struct phy *phy; member
81 /* Per-slot PERST# */
86 /* Per-slot clkreq */
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| D | pcie-intel-gw.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Intel Gateway SoCs
14 #include <linux/phy/phy.h>
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
26 /* PCIe Application logic Registers */
70 struct phy *phy; member
84 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
86 writel(val, pcie->app_base + ofs); in pcie_app_wr()
89 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
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| D | pcie-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for UniPhier SoCs
19 #include <linux/phy/phy.h>
23 #include "pcie-designware.h"
69 struct phy *phy; member
73 #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev)
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
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| /linux-6.12.1/drivers/pci/controller/plda/ |
| D | pcie-starfive.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for StarFive JH7110 Soc.
20 #include <linux/phy/phy.h>
27 #include "pcie-plda.h"
60 struct phy *phy; member
67 * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory
68 * space. PCIe read and write requests targeting BAR0/1 are routed to so called
105 static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, in starfive_pcie_parse_dt() argument
110 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); in starfive_pcie_parse_dt()
111 if (pcie->num_clks < 0) in starfive_pcie_parse_dt()
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| /linux-6.12.1/drivers/pci/controller/ |
| D | pcie-mediatek-gen3.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
11 #include <linux/clk-provider.h>
23 #include <linux/phy/phy.h>
71 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
75 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
79 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
113 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
123 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
129 * struct mtk_gen3_pcie_pdata - differentiate between host generations
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| D | pcie-mt7621.c | 1 // SPDX-License-Identifier: GPL-2.0+
12 * support RT2880/RT3883 PCIe
15 * support RT6855/MT7620 PCIe
28 #include <linux/phy/phy.h>
35 /* MediaTek-specific configuration registers */
40 /* Host-PCI bridge registers */
48 /* PCIe RC control registers */
67 * struct mt7621_pcie_port - PCIe port information
70 * @pcie: pointer to PCIe host info
72 * @phy: pointer to PHY control block
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| D | pcie-iproc-platform.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/phy/phy.h>
19 #include "pcie-iproc.h"
23 .compatible = "brcm,iproc-pcie",
26 .compatible = "brcm,iproc-pcie-paxb-v2",
29 .compatible = "brcm,iproc-pcie-paxc",
32 .compatible = "brcm,iproc-pcie-paxc-v2",
41 struct device *dev = &pdev->dev; in iproc_pltfm_pcie_probe()
42 struct iproc_pcie *pcie; in iproc_pltfm_pcie_probe() local
43 struct device_node *np = dev->of_node; in iproc_pltfm_pcie_probe()
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| D | pcie-xilinx-nwl.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
21 #include <linux/pci-ecam.h>
22 #include <linux/phy/phy.h>
34 /* Egress - Bridge translation registers */
44 /* Ingress - address translations */
52 /* Rxed msg fifo - Interrupt status registers */
161 struct phy *phy[4]; member
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| /linux-6.12.1/drivers/phy/broadcom/ |
| D | phy-bcm-cygnus-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/phy/phy.h>
24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device
25 * @core: pointer to the Cygnus PCIe PHY core control
26 * @id: internal ID to identify the Cygnus PCIe PHY
27 * @phy: pointer to the kernel PHY device
32 struct phy *phy; member
36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control
40 * @phys: pointer to Cygnus PHY device
49 static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable) in cygnus_pcie_power_config() argument
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| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
12 #include <linux/phy/phy.h>
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
43 * @index: PHY index
44 * @phy: pointer to the kernel PHY device
49 struct phy *phy; member
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
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| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | brcm,iproc-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,iproc-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom iProc PCIe controller with the platform bus interface
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
14 - $ref: /schemas/pci/pci-host-bridge.yaml#
19 - enum:
22 - brcm,iproc-pcie
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| D | mediatek-pcie-gen3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
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| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
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