Searched full:parent1 (Results 1 – 5 of 5) sorted by relevance
| /linux-6.12.1/drivers/clk/davinci/ |
| D | da8xx-cfgchip.c | 198 const char *parent1; member
242 const char * const parent_names[] = { info->parent0, info->parent1 }; in da8xx_cfgchip_mux_clk_register()
272 .parent1 = "div4.5",
294 .parent1 = "pll1_sysclk2",
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| /linux-6.12.1/drivers/clk/ |
| D | clk-milbeaut.c | 35 #define M10V_SPI_PARENT1 "spi-parent1"
38 #define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
41 #define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
43 #define M10V_NFCLK_PARENT1 "nfclk-parent1"
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| D | clk_test.c | 555 struct clk *parent1, *parent2; in clk_test_multiple_parents_mux_set_range_set_parent_get_rate() local
561 parent1 = clk_hw_get_clk_kunit(test, &ctx->parents_ctx[0].hw, NULL); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
562 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent1); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
563 KUNIT_ASSERT_TRUE(test, clk_is_match(clk_get_parent(clk), parent1)); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
568 ret = clk_set_rate(parent1, DUMMY_CLOCK_RATE_1); in clk_test_multiple_parents_mux_set_range_set_parent_get_rate()
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | rockchip-isp1.yaml | 264 parent1: parent {
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| /linux-6.12.1/security/landlock/ |
| D | fs.c | 450 * restrictions(parent1) >= restrictions(child2) in no_more_access()
731 * @dentry_child1: Dentry to the initial child of the parent1 path. This
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