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/linux-6.12.1/drivers/clk/
Dclk-renesas-pcie.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
110 return -EIO; in rs9_regmap_i2c_write()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
Ddce120_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
36 /*ClocksStateInvalid - should not be used*/
38 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
48 * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
51 * Reads from VBIOS the XGMI spread spectrum info and saves it within
54 * sets the ->xgmi_enabled flag.
60 struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios; in dce121_clock_patch_xgmi_ss_info()
62 clk_mgr_dce->xgmi_enabled = false; in dce121_clock_patch_xgmi_ss_info()
64 result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI, in dce121_clock_patch_xgmi_ss_info()
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Drenesas,9series.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 9-series I2C PCIe clock generators
10 The Renesas 9-series are I2C PCIe clock generators providing
16 - 9FGV0241:
17 0 -- DIF0
18 1 -- DIF1
19 - 9FGV0441:
20 0 -- DIF0
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/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu11_driver_if_sienna_cichlid.h19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
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Dsmu11_driver_if_arcturus.h19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
45 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
46 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
47 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
48 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
50 #define MAX_FCLK_DPM_LEVEL (NUM_FCLK_DPM_LEVELS - 1)
51 #define MAX_XGMI_LEVEL (NUM_XGMI_LEVELS - 1)
52 #define MAX_XGMI_PSTATE_LEVEL (NUM_XGMI_PSTATE_LEVELS - 1)
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Dsmu13_driver_if_aldebaran.h19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
110 // These are aligned with the out of band monitor alarm bits for common throttlers
268 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
269 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
388 uint32_t ApccPlusResidencyLimit; //PCC residency % (0-100)
425 // UCLK Spread Spectrum
430 // FCLK Spread Spectrum
467 // Padding - ignore
502 // Padding - ignore
Dsmu11_driver_if_navi10.h19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
51 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
52 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
53 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
54 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
55 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
56 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
57 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
58 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
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Dsmu14_driver_if_v14_0.h19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
517 uint8_t SnapToDiscrete; // 0 - Fine grained DPM, 1 - Discrete DPM
520 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
1106 …uint16_t Vmin_Hot_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1107 …uint16_t Vmin_Cold_T0[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Initial (pre-aging) Vse…
1108 …uint16_t Vmin_Hot_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be …
1109 …uint16_t Vmin_Cold_Eol[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) End-of-life Vset to be …
1110 uint16_t Vmin_Aging_Offset[PMFW_VOLT_PLANE_COUNT]; //In mV(Q2) Worst-case aging margin
1116 …//Linear offset or GB term to account for mis-correlation between PSM and Vmin shift trends across…
1221 … FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:Div-1/8
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/linux-6.12.1/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c5 * Copyright 2007-2009 Stuart Bennett
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
58 * this does not give a correct answer for off-chip dvi, but there's no in nv04_dfp_get_bound_head()
61 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_get_bound_head()
72 * Luckily we do know the values ;-) in nv04_dfp_bind_head()
78 int ramdac = (dcbent->or & DCB_OUTPUT_C) >> 2; in nv04_dfp_bind_head()
84 if (dcbent->type == DCB_OUTPUT_LVDS) in nv04_dfp_bind_head()
87 nv_write_tmds(dev, dcbent->or, 0, 0x04, tmds04); in nv04_dfp_bind_head()
90 nv_write_tmds(dev, dcbent->or, 1, 0x04, tmds04 ^ 0x08); in nv04_dfp_bind_head()
95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
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/linux-6.12.1/drivers/gpu/drm/amd/display/include/
Dddc_service_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
101 capabilities going OUT OF SOURCE DEVICE (link capabilities)
103 /* support for Spread Spectrum(SS) */
105 /* DP link settings (laneCount, linkRate, Spread) */
111 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
213 /* Input: Enable spread spectrum */
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
234 /* VBIOS returns a fixed display clock when DFS-bypass feature
285 /* 1 = Center Spread; 0 = down spread */
289 /* 1 = delta-sigma type parameter; 0 = ver1 */
/linux-6.12.1/drivers/scsi/isci/
Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 * Down-spreading SSC (only method allowed for SATA):
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6q-cubox-i.dts4 * This file is dual-licensed: you can use it either under the terms
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-brcm.dtsi"
46 #include "imx6qdl-cubox-i.dtsi"
49 model = "SolidRun Cubox-i Dual/Quad";
50 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
55 fsl,transmit-level-mV = <1104>;
56 fsl,transmit-boost-mdB = <0>;
[all …]
Dimx6q-cubox-i-som-v15.dts4 * This file is dual-licensed: you can use it either under the terms
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-ti.dtsi"
46 #include "imx6qdl-cubox-i.dtsi"
49 model = "SolidRun Cubox-i Dual/Quad (1.5som)";
50 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
55 fsl,transmit-level-mV = <1104>;
56 fsl,transmit-boost-mdB = <0>;
[all …]
Dimx6q-cubox-i-emmc-som-v15.dts4 * This file is dual-licensed: you can use it either under the terms
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 /dts-v1/;
44 #include "imx6qdl-sr-som.dtsi"
45 #include "imx6qdl-sr-som-ti.dtsi"
46 #include "imx6qdl-sr-som-emmc.dtsi"
47 #include "imx6qdl-cubox-i.dtsi"
50 model = "SolidRun Cubox-i Dual/Quad (1.5som+emmc)";
51 compatible = "solidrun,cubox-i/q", "fsl,imx6q";
56 fsl,transmit-level-mV = <1104>;
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Dimx6q-hummingboard2-emmc-som-v15.dts3 * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
6 * This file is dual-licensed: you can use it either under the terms
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 /dts-v1/;
47 #include "imx6qdl-sr-som.dtsi"
48 #include "imx6qdl-sr-som-emmc.dtsi"
49 #include "imx6qdl-sr-som-ti.dtsi"
50 #include "imx6qdl-hummingboard2.dtsi"
59 fsl,transmit-level-mV = <1104>;
60 fsl,transmit-boost-mdB = <0>;
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Dimx6q-hummingboard2.dts2 * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
5 * This file is dual-licensed: you can use it either under the terms
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 /dts-v1/;
45 #include "imx6qdl-sr-som.dtsi"
46 #include "imx6qdl-sr-som-brcm.dtsi"
47 #include "imx6qdl-hummingboard2.dtsi"
48 #include "imx6qdl-hummingboard2-emmc.dtsi"
57 fsl,transmit-level-mV = <1104>;
58 fsl,transmit-boost-mdB = <0>;
[all …]
Dimx6q-hummingboard2-som-v15.dts3 * Copyright (C) 2015 Rabeeh Khoury <rabeeh@solid-run.com>
6 * This file is dual-licensed: you can use it either under the terms
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 /dts-v1/;
47 #include "imx6qdl-sr-som.dtsi"
48 #include "imx6qdl-sr-som-ti.dtsi"
49 #include "imx6qdl-hummingboard2.dtsi"
58 fsl,transmit-level-mV = <1104>;
59 fsl,transmit-boost-mdB = <0>;
60 fsl,transmit-atten-16ths = <9>;
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/linux-6.12.1/drivers/usb/dwc3/
Ddwc3-octeon.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2017 Cavium Networks
24 /* BIST fast-clear mode select. A BIST run with this bit set
39 /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
41 /* Spread-spectrum clock modulation range:
42 * 0x0 = -4980 ppm downspread
43 * 0x1 = -4492 ppm downspread
44 * 0x2 = -4003 ppm downspread
45 * 0x3 - 0x7 = Reserved
48 /* Enable non-standard oscillator frequencies:
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dphy-cadence-sierra.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Swapnil Jakhade <sjakhade@cadence.com>
15 - Yuti Amonkar <yamonkar@cadence.com>
20 - cdns,sierra-phy-t0
21 - ti,sierra-phy-t0
23 '#address-cells':
26 '#size-cells':
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Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j7200-serdes-10g
24 - ti,j721e-serdes-10g
26 '#address-cells':
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/linux-6.12.1/drivers/gpu/drm/amd/include/
Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
609 … uint32_t pspbl_init_done_check_timeout; // time out in unit of us when polling pspbl init done
[all …]
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
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/linux-6.12.1/drivers/phy/xilinx/
Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
198 * struct xpsgtr_phy - representation of a lane
219 * struct xpsgtr_dev - representation of a ZynMP GT device
225 * @refclk_sscs: spread spectrum settings for the reference clocks
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/linux-6.12.1/drivers/gpu/drm/radeon/
Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
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