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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn35/
Ddcn35_resource.h1 /* SPDX-License-Identifier: MIT */
49 #define OPP_REG_LIST_DCN20_RI(id) \ argument
50 OPP_REG_LIST_DCN10_RI(id), \
51 OPP_DPG_REG_LIST_RI(id), \
52 SRI_ARR(FMT_422_CONTROL, FMT, id), \
53 SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)
55 #define OPP_REG_LIST_DCN35_RI(id) \ argument
56 OPP_REG_LIST_DCN20_RI(id), \
57 SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)
59 #define VPG_DCN31_REG_LIST_RI(id) \ argument
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn401/
Ddcn401_resource.h1 // SPDX-License-Identifier: MIT
34 #define HUBP_REG_LIST_DCN401_RI(id) \ argument
35 SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \
36 SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \
37 SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \
38 SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \
39 SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id), \
40 SRI_ARR(DCHUBP_CNTL, HUBP, id), \
41 SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \
42 SRI_ARR(HUBPREQ_DEBUG, HUBP, id), \
[all …]
/linux-6.12.1/drivers/usb/phy/
Dphy-mv-usb.c1 // SPDX-License-Identifier: GPL-2.0+
21 #include <linux/usb/otg.h>
26 #include "phy-mv-usb.h"
28 #define DRIVER_DESC "Marvell USB OTG transceiver driver"
33 static const char driver_name[] = "mv-otg";
52 static int mv_otg_set_vbus(struct usb_otg *otg, bool on) in mv_otg_set_vbus() argument
54 struct mv_otg *mvotg = container_of(otg->usb_phy, struct mv_otg, phy); in mv_otg_set_vbus()
55 if (mvotg->pdata->set_vbus == NULL) in mv_otg_set_vbus()
56 return -ENODEV; in mv_otg_set_vbus()
58 return mvotg->pdata->set_vbus(on); in mv_otg_set_vbus()
[all …]
Dphy-fsl-usb.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Jerry Huang <Chang-Ming.Huang@freescale.com>
32 #include "phy-fsl-usb.h"
43 #define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
46 static const char driver_name[] = "fsl-usb2-otg";
109 fsl_writel(temp, &usb_dr_regs->ulpiview); in write_ulpi()
113 /* -------------------------------------------------------------*/
114 /* Operations that will be called from OTG Finite State Machine */
121 tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK; in fsl_otg_chrg_vbus()
131 fsl_writel(tmp, &usb_dr_regs->otgsc); in fsl_otg_chrg_vbus()
[all …]
Dphy-ulpi.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <linux/usb/otg.h>
22 unsigned int id; member
29 .id = (_id), \
47 if (phy->flags & ULPI_OTG_ID_PULLUP) in ulpi_set_otg_flags()
54 if (phy->flags & ULPI_OTG_DP_PULLDOWN_DIS) in ulpi_set_otg_flags()
57 if (phy->flags & ULPI_OTG_DM_PULLDOWN_DIS) in ulpi_set_otg_flags()
60 if (phy->flags & ULPI_OTG_EXTVBUSIND) in ulpi_set_otg_flags()
74 if (phy->flags & ULPI_FC_HS) in ulpi_set_fc_flags()
76 else if (phy->flags & ULPI_FC_LS) in ulpi_set_fc_flags()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h1 /* Copyright 2012-15 Advanced Micro Devices, Inc.
33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ argument
34 SRI(RESYNC_CNTL, PIXCLK, id), \
35 SRI(PLL_CNTL, BPHYC_PLL, id)
37 #define CS_COMMON_REG_LIST_DCE_80(id) \ argument
38 SRI(RESYNC_CNTL, PIXCLK, id), \
39 SRI(PLL_CNTL, DCCG_PLL, id)
41 #define CS_COMMON_REG_LIST_DCE_112(id) \ argument
42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id)
72 SRII(PIXEL_RATE_CNTL, OTG, 0),\
[all …]
/linux-6.12.1/drivers/phy/samsung/
Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
13 #include "phy-samsung-usb2.h"
168 return -EINVAL; in exynos5250_rate_to_clk()
176 struct samsung_usb2_phy_driver *drv = inst->drv; in exynos5250_isol()
180 if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol()
181 inst->cfg->id == EXYNOS5250_DEVICE) in exynos5250_isol()
183 else if (drv->cfg == &exynos5250_usb2_phy_config && in exynos5250_isol()
184 inst->cfg->id == EXYNOS5250_HOST) in exynos5250_isol()
186 else if (drv->cfg == &exynos5420_usb2_phy_config && in exynos5250_isol()
[all …]
/linux-6.12.1/drivers/usb/common/
Dusb-otg-fsm.c1 // SPDX-License-Identifier: GPL-2.0+
3 * OTG Finite State Machine from OTG spec
8 * Jerry Huang <Chang-Ming.Huang@freescale.com>
18 #include <linux/usb/otg.h>
19 #include <linux/usb/otg-fsm.h>
33 if (fsm->protocol != protocol) { in otg_set_protocol()
34 VDBG("Changing role fsm->protocol= %d; new protocol= %d\n", in otg_set_protocol()
35 fsm->protocol, protocol); in otg_set_protocol()
37 if (fsm->protocol == PROTO_HOST) in otg_set_protocol()
39 else if (fsm->protocol == PROTO_GADGET) in otg_set_protocol()
[all …]
/linux-6.12.1/drivers/usb/core/
Dotg_productlist.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * This OTG and Embedded Host list is "Targeted Peripheral List".
13 /* hubs are optional in OTG, but very handy ... */
27 /* Linux-USB CDC Ethernet gadget */
29 /* Linux-USB CDC Ethernet + RNDIS gadget */
43 struct usb_device_id *id = productlist_table; in is_targeted() local
45 /* HNP test device is _never_ targeted (see OTG spec 6.6.6) */ in is_targeted()
46 if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a && in is_targeted()
47 le16_to_cpu(dev->descriptor.idProduct) == 0xbadd)) in is_targeted()
50 /* OTG PET device is always targeted (see OTG 2.0 ECN 6.4.2) */ in is_targeted()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Drockchip,inno-usb2phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3128-usb2phy
17 - rockchip,rk3228-usb2phy
18 - rockchip,rk3308-usb2phy
19 - rockchip,rk3328-usb2phy
[all …]
Dallwinner,suniv-f1c100s-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,suniv-f1c100s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,suniv-f1c100s-usb-phy
24 reg-names:
29 description: USB OTG PHY bus clock
[all …]
Dallwinner,sun8i-v3s-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun8i-v3s-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
Dallwinner,sun5i-a13-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun5i-a13-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU1 registers
[all …]
Dallwinner,sun8i-a23-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-a23-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun8i-a23-usb-phy
20 - allwinner,sun8i-a33-usb-phy
24 - description: PHY Control registers
[all …]
Dallwinner,sun50i-a64-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-a64-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - allwinner,sun20i-d1-usb-phy
20 - allwinner,sun50i-a64-usb-phy
24 - description: PHY Control registers
[all …]
Dallwinner,sun50i-h6-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun50i-h6-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun50i-h6-usb-phy
22 - description: PHY Control registers
23 - description: PHY PMU0 registers
[all …]
/linux-6.12.1/drivers/usb/dwc3/
Ddrd.c1 // SPDX-License-Identifier: GPL-2.0
3 * drd.c - DesignWare USB3 DRD Controller Dual-role support
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com
21 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_disable_events()
24 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_disable_events()
29 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVTEN); in dwc3_otg_enable_events()
32 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_enable_events()
37 u32 reg = dwc3_readl(dwc->regs, DWC3_OEVT); in dwc3_otg_clear_events()
39 dwc3_writel(dwc->regs, DWC3_OEVTEN, reg); in dwc3_otg_clear_events()
56 spin_lock(&dwc->lock); in dwc3_otg_thread_irq()
[all …]
/linux-6.12.1/drivers/usb/chipidea/
Dotg_fsm.c1 // SPDX-License-Identifier: GPL-2.0
3 * otg_fsm.c - ChipIdea USB IP core OTG FSM driver
11 * This file mainly handles OTG fsm, it includes OTG fsm operations
15 * - ADP
16 * - OTG test device
19 #include <linux/usb/otg.h>
27 #include "otg.h"
30 /* Add for otg: interact with user space app */
40 t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req); in a_bus_req_show()
41 size -= t; in a_bus_req_show()
[all …]
Dotg.c1 // SPDX-License-Identifier: GPL-2.0
3 * otg.c - ChipIdea USB IP core OTG driver
11 * This file mainly handles otgsc register, OTG fsm operations for HNP and SRP
15 #include <linux/usb/otg.h>
21 #include "otg.h"
25 * hw_read_otgsc - returns otgsc register bits value.
35 * If using extcon framework for VBUS and/or ID signal in hw_read_otgsc()
38 cable = &ci->platdata->vbus_extcon; in hw_read_otgsc()
39 if (!IS_ERR(cable->edev) || ci->role_switch) { in hw_read_otgsc()
40 if (cable->changed) in hw_read_otgsc()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/usb/
Ddwc2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/dwc2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DesignWare HS OTG USB 2.0 controller
10 - Rob Herring <robh@kernel.org>
13 - $ref: usb-drd.yaml#
14 - $ref: usb-hcd.yaml#
19 - const: brcm,bcm2835-usb
20 - const: hisilicon,hi6220-usb
[all …]
Dusb-drd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-drd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic USB OTG Controller
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 otg-rev:
15 Tells usb driver the release number of the OTG and EH supplement with
16 which the device and its descriptors are compliant, in binary-coded
17 decimal (i.e. 2.0 is 0200H). This property is used if any real OTG
[all …]
/linux-6.12.1/include/linux/platform_data/
Dmv_usb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
25 struct mv_usb_addon_irq *id; /* Only valid for OTG. ID pin change*/ member
26 struct mv_usb_addon_irq *vbus; /* valid for OTG/UDC. VBUS change*/
28 /* only valid for HCD. OTG or Host only*/
31 /* This flag is used for that needs id pin checked by otg */
/linux-6.12.1/drivers/usb/musb/
Dda8xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments DA8xx/OMAP-L1x "glue layer"
5 * Copyright (c) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 * Copyright (C) 2005-2006 by Texas Instruments
24 #include <linux/dma-mapping.h>
33 /* USB 2.0 OTG module registers */
47 #define DA8XX_USB_GENERIC_RNDIS_EP_SIZE_REG(n) (0x50 + (((n) - 1) << 2))
77 * - not read/write INTRUSB/INTRUSBE (except during
79 * - use INTSET/INTCLR instead.
83 * da8xx_musb_enable - enable interrupts
[all …]
Dtusb6010.c1 // SPDX-License-Identifier: GPL-2.0
3 * TUSB6010 USB 2.0 OTG Dual Role controller
9 * - Driver assumes that interface to external host (main CPU) is
27 #include <linux/dma-mapping.h>
51 void __iomem *tbase = musb->ctrl_base; in tusb_get_revision()
68 void __iomem *tbase = musb->ctrl_base; in tusb_print_revision()
71 rev = musb->tusb_revision; in tusb_print_revision()
96 * Workaround for spontaneous WBUS wake-up issue #2 for tusb3.0.
101 void __iomem *tbase = musb->ctrl_base; in tusb_wbus_quirk()
114 dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n", in tusb_wbus_quirk()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/extcon/
Dextcon-max3355.txt1 Maxim Integrated MAX3355 USB OTG chip
2 -------------------------------------
5 integrated USB OTG dual-role transceiver to function as a USB OTG dual-role
9 - compatible: should be "maxim,max3355";
10 - maxim,shdn-gpios: should contain a phandle and GPIO specifier for the GPIO pin
12 - id-gpios: should contain a phandle and GPIO specifier for the GPIO pin
17 usb-otg {
19 maxim,shdn-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
20 id-gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>;

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