Searched +full:opp +full:- +full:table +full:- +full:2 (Results 1 – 25 of 313) sorted by relevance
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/linux-6.12.1/arch/arm64/boot/dts/apple/ |
D | t600x-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 5 * Other names: H13J, "Jade Chop", "Jade", "Jade 2C" 11 #address-cells = <2>; 12 #size-cells = <2>; 15 #address-cells = <2>; 16 #size-cells = <0>; 18 cpu-map { 63 enable-method = "spin-table"; 64 cpu-release-addr = <0 0>; /* To be filled by loader */ 65 next-level-cache = <&l2_cache_0>; [all …]
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D | t8112.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/apple-aic.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/pinctrl/apple.h> 14 #include <dt-bindings/spmi/spmi.h> 17 compatible = "apple,t8112", "apple,arm-platform"; 19 #address-cells = <2>; 20 #size-cells = <2>; 23 #address-cells = <2>; [all …]
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D | t8103.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-bindings/interrupt-controller/apple-aic.h> 12 #include <dt-bindings/interrupt-controller/irq.h> 13 #include <dt-bindings/pinctrl/apple.h> 16 compatible = "apple,t8103", "apple,arm-platform"; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <2>; 23 #size-cells = <0>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/opp/ |
D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states [all …]
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D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Technologies, Inc. NVMEM OPP 10 - Ilia Lin <ilia.lin@kernel.org> 13 - $ref: opp-v2-base.yaml# 17 the CPU frequencies subset and voltage value of each OPP varies based on 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). [all …]
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D | opp-v2-base.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) Common Properties 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 Devices work at voltage-current-frequency combinations and some implementations 25 pattern: '^opp-table(-[a-z0-9]+)?$' 27 opp-shared: 29 Indicates that device nodes using this OPP Table Node's phandle switch [all …]
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/linux-6.12.1/drivers/opp/ |
D | opp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Generic OPP Interface 5 * Copyright (C) 2009-2010 Texas Instruments Incorporated. 26 /* Lock to allow exclusive modification to the device and opp lists */ 31 /* OPP Config flags */ 34 #define OPP_CONFIG_REGULATOR_HELPER BIT(2) 41 * struct opp_config_data - data for set config operations 42 * @opp_table: OPP table 43 * @flags: OPP config flags 45 * This structure stores the OPP config information for each OPP table [all …]
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D | of.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Generic OPP OF helpers 5 * Copyright (C) 2009-2010 Texas Instruments Incorporated. 22 #include "opp.h" 24 /* OPP tables with uninitialized required OPPs, protected by opp_table_lock */ 28 * Returns opp descriptor node for a device node, caller must 34 /* "operating-points-v2" can be an array for power domain providers */ in _opp_of_get_opp_desc_node() 35 return of_parse_phandle(np, "operating-points-v2", index); in _opp_of_get_opp_desc_node() 38 /* Returns opp descriptor node for a device, caller must do of_node_put() */ 41 return _opp_of_get_opp_desc_node(dev->of_node, 0); in dev_pm_opp_of_get_opp_desc_node() [all …]
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D | ti-opp-supply.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/ 5 * Dave Gerlach <d-gerlach@ti.com> 7 * TI OPP supply driver that provides override into the regulator control 8 * for generic opp core to handle devices with ABB regulator and/or 26 * struct ti_opp_supply_optimum_voltage_table - optimized voltage table 36 * struct ti_opp_supply_data - OMAP specific opp supply data 37 * @vdd_table: Optimized voltage mapping table 40 * @old_supplies: Placeholder for supplies information for old OPP. 41 * @new_supplies: Placeholder for supplies information for new OPP. [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/power/ |
D | qcom,rpmpd.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bjorn Andersson <andersson@kernel.org> 19 - enum: 20 - qcom,mdm9607-rpmpd 21 - qcom,msm8226-rpmpd 22 - qcom,msm8909-rpmpd 23 - qcom,msm8916-rpmpd 24 - qcom,msm8917-rpmpd [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/cpufreq/ |
D | qcom-cpufreq-nvmem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ilia Lin <ilia.lin@kernel.org> 17 on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level 18 according to the required OPPs defined in the CPU OPP tables. 20 For old implementation efuses are parsed to select the correct opp table and 28 - qcom,apq8064 29 - qcom,apq8096 [all …]
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D | apple,cluster-cpufreq.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Hector Martin <marcan@marcan.st> 13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of 15 operating-points-v2 table to define the CPU performance states, with the 16 opp-level property specifying the hardware p-state index for that level. 21 - items: 22 - enum: [all …]
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/linux-6.12.1/arch/arm/boot/dts/samsung/ |
D | exynos5422-odroid-core.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source 6 * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. 10 #include <dt-bindings/clock/samsung,s2mps11.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/gpio/gpio.h> 14 #include "exynos5422-cpus.dtsi" 27 stdout-path = "serial2:115200n8"; 31 compatible = "samsung,secure-firmware"; 35 fixed-rate-clocks { [all …]
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D | exynos4210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2010-2011 Linaro Ltd. 20 #include "exynos4-cpu-thermal.dtsi" 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-names = "bus"; 35 operating-points-v2 = <&bus_acp_opp_table>; 38 bus_acp_opp_table: opp-table { 39 compatible = "operating-points-v2"; [all …]
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D | exynos4x12.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 19 #include "exynos4-cpu-thermal.dtsi" 27 fimc-lite0 = &fimc_lite_0; 28 fimc-lite1 = &fimc_lite_1; 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-names = "bus"; 35 operating-points-v2 = <&bus_acp_opp_table>; 38 bus_acp_opp_table: opp-table { 39 compatible = "operating-points-v2"; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/exynos/ |
D | exynos5433-bus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 11 compatible = "samsung,exynos-bus"; 13 clock-names = "bus"; 14 operating-points-v2 = <&bus_g2d_400_opp_table>; 19 compatible = "samsung,exynos-bus"; 21 clock-names = "bus"; 22 operating-points-v2 = <&bus_g2d_266_opp_table>; 27 compatible = "samsung,exynos-bus"; 29 clock-names = "bus"; 30 operating-points-v2 = <&bus_gscl_opp_table>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
D | rk3399-op1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <800000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; 20 opp-microvolt = <825000>; [all …]
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D | rk3399-t.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 #include "rk3399-base.dtsi" 10 cluster0_opp: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 15 opp-hz = /bits/ 64 <408000000>; 16 opp-microvolt = <875000 875000 1250000>; 17 clock-latency-ns = <40000>; 20 opp-hz = /bits/ 64 <600000000>; [all …]
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D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 6 #include "rk3399-base.dtsi" 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <825000 825000 1250000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/gpu/ |
D | arm,mali-midgard.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only 3 --- 4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 14 pattern: '^gpu@[a-f0-9]+$' 17 - items: 18 - enum: 19 - samsung,exynos5250-mali 20 - const: arm,mali-t604 [all …]
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | omap34xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/media/omap3-isp.h> 16 /* OMAP343x/OMAP35xx variants OPP1-6 */ 17 operating-points-v2 = <&cpu0_opp_table>; 19 clock-latency = <300000>; /* From legacy driver */ 20 #cooling-cells = <2>; 24 cpu0_opp_table: opp-table { 25 compatible = "operating-points-v2-ti-cpu"; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/interconnect/ |
D | qcom,msm8998-bwmon.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 17 - Measuring the bandwidth between CPUs and Last Level Cache Controller - 19 - Measuring the bandwidth between Last Level Cache Controller and memory 20 (DDR) - called LLCC BWMON. 25 - const: qcom,msm8998-bwmon # BWMON v4 26 - items: [all …]
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D | mediatek,cci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jia-Wei Chang <jia-wei.chang@mediatek.com> 11 - Johnson Wang <johnson.wang@mediatek.com> 21 - mediatek,mt8183-cci 22 - mediatek,mt8186-cci 26 - description: 28 - description: 33 clock-names: [all …]
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/linux-6.12.1/drivers/ufs/host/ |
D | ufshcd-pltfrm.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 2011-2013 Samsung India Software Operations 19 #include "ufshcd-pltfrm.h" 22 #define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2 29 struct device *dev = hba->dev; in ufshcd_parse_clock_info() 30 struct device_node *np = dev->of_node; in ufshcd_parse_clock_info() 39 cnt = of_property_count_strings(np, "clock-names"); in ufshcd_parse_clock_info() 40 if (!cnt || (cnt == -EINVAL)) { in ufshcd_parse_clock_info() 52 sz = of_property_count_u32_elems(np, "freq-table-hz"); in ufshcd_parse_clock_info() 54 dev_info(dev, "freq-table-hz property not specified\n"); in ufshcd_parse_clock_info() [all …]
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/linux-6.12.1/drivers/cpufreq/ |
D | qcom-cpufreq-hw.c | 1 // SPDX-License-Identifier: GPL-2.0 7 #include <linux/clk-provider.h> 27 #define CLK_HW_DIV 2 30 #define GT_IRQ_STATUS BIT(2) 50 * Mutex to synchronize between de-init sequence and re-starting LMh 76 struct dev_pm_opp *opp; in qcom_cpufreq_set_bw() local 80 dev = get_cpu_device(policy->cpu); in qcom_cpufreq_set_bw() 82 return -ENODEV; in qcom_cpufreq_set_bw() 84 opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true); in qcom_cpufreq_set_bw() 85 if (IS_ERR(opp)) in qcom_cpufreq_set_bw() [all …]
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