Searched +full:opp +full:- +full:supported +full:- +full:hw (Results 1 – 25 of 111) sorted by relevance
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/linux-6.12.1/arch/arm/boot/dts/nvidia/ |
D | tegra124-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 emc_icc_dvfs_opp_table: opp-table-emc { 5 compatible = "operating-points-v2"; 7 opp-12750000-800 { 8 opp-microvolt = <800000 800000 1150000>; 9 opp-hz = /bits/ 64 <12750000>; 10 opp-supported-hw = <0x0003>; 13 opp-12750000-950 { 14 opp-microvolt = <950000 950000 1150000>; 15 opp-hz = /bits/ 64 <12750000>; [all …]
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D | tegra30-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 core_opp_table: opp-table-core { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 core_opp_950: opp-950000 { 9 opp-microvolt = <950000 950000 1350000>; 10 opp-level = <950000>; 13 core_opp_1000: opp-1000000 { 14 opp-microvolt = <1000000 1000000 1350000>; 15 opp-level = <1000000>; [all …]
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D | tegra20-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 core_opp_table: opp-table-core { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 core_opp_950: opp-950000 { 9 opp-microvolt = <950000 950000 1300000>; 10 opp-level = <950000>; 13 core_opp_1000: opp-1000000 { 14 opp-microvolt = <1000000 1000000 1300000>; 15 opp-level = <1000000>; [all …]
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D | tegra30-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 cpu0_opp_table: opp-table-cpu0 { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 opp-51000000-800 { 9 clock-latency-ns = <100000>; 10 opp-supported-hw = <0x1F 0x31FE>; 11 opp-hz = /bits/ 64 <51000000>; 14 opp-51000000-850 { 15 clock-latency-ns = <100000>; [all …]
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D | tegra20-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 cpu0_opp_table: opp-table-cpu0 { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 opp-216000000-750 { 9 clock-latency-ns = <400000>; 10 opp-supported-hw = <0x0F 0x0003>; 11 opp-hz = /bits/ 64 <216000000>; 12 opp-suspend; 15 opp-216000000-800 { [all …]
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/linux-6.12.1/arch/arm64/boot/dts/nvidia/ |
D | tegra132-peripherals-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 4 /* EMC DVFS OPP table */ 5 emc_icc_dvfs_opp_table: opp-table-dvfs0 { 6 compatible = "operating-points-v2"; 8 opp-12750000-800 { 9 opp-microvolt = <800000 800000 1150000>; 10 opp-hz = /bits/ 64 <12750000>; 11 opp-supported-hw = <0x0003>; 14 opp-12750000-950 { 15 opp-microvolt = <950000 950000 1150000>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/qcom/ |
D | msm8996pro.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 9 /delete-node/ opp-table-cluster0; 10 /delete-node/ opp-table-cluster1; 14 * nibble of supported hw, so speed bin 0 becomes 0x10, speed bin 1 18 cluster0_opp: opp-table-cluster0 { 19 compatible = "operating-points-v2-kryo-cpu"; 20 nvmem-cells = <&speedbin_efuse>; 21 opp-shared; 23 opp-307200000 { 24 opp-hz = /bits/ 64 <307200000>; [all …]
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D | sdm660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 13 compatible = "qcom,adreno-512.0", "qcom,adreno"; 14 operating-points-v2 = <&gpu_sdm660_opp_table>; 16 gpu_sdm660_opp_table: opp-table { 17 compatible = "operating-points-v2"; 23 * at the same opp-level 25 opp-750000000 { 26 opp-hz = /bits/ 64 <750000000>; 27 opp-level = <RPM_SMD_LEVEL_TURBO>; 28 opp-peak-kBps = <5412000>; [all …]
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D | msm8996.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/qcom,gcc-msm8996.h> 8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h> 9 #include <dt-bindings/clock/qcom,rpmcc.h> 10 #include <dt-bindings/interconnect/qcom,msm8996.h> 11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h> 12 #include <dt-bindings/firmware/qcom,scm.h> 13 #include <dt-bindings/gpio/gpio.h> [all …]
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/linux-6.12.1/arch/arm64/boot/dts/allwinner/ |
D | sun50i-h616-cpu-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 cpu_opp_table: opp-table-cpu { 6 compatible = "allwinner,sun50i-h616-operating-points"; 7 nvmem-cells = <&cpu_speed_grade>; 8 opp-shared; 10 opp-480000000 { 11 opp-hz = /bits/ 64 <480000000>; 12 opp-microvolt = <900000>; 13 clock-latency-ns = <244144>; /* 8 32k periods */ 14 opp-supported-hw = <0x3f>; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/opp/ |
D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI CPU OPP (Operating Performance Points) 12 OPP vary based on the silicon variant used. The data sheet sections 18 This document extends the operating-points-v2 binding by providing 22 - Dhruva Gole <d-gole@ti.com> 25 - $ref: opp-v2-base.yaml# 29 const: operating-points-v2-ti-cpu [all …]
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D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Technologies, Inc. NVMEM OPP 10 - Ilia Lin <ilia.lin@kernel.org> 13 - $ref: opp-v2-base.yaml# 17 the CPU frequencies subset and voltage value of each OPP varies based on 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). [all …]
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D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner H6 CPU OPP 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 15 OPP varies based on the silicon variant in use. Allwinner Process 20 - $ref: opp-v2-base.yaml# 25 - allwinner,sun50i-h6-operating-points [all …]
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D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states [all …]
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D | opp-v2-base.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) Common Properties 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 Devices work at voltage-current-frequency combinations and some implementations 25 pattern: '^opp-table(-[a-z0-9]+)?$' 27 opp-shared: 29 Indicates that device nodes using this OPP Table Node's phandle switch [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/cpufreq/ |
D | imx-cpufreq-dt.txt | 1 i.MX CPUFreq-DT OPP bindings 6 the opp-supported-hw values for each OPP to check if the OPP is allowed. 9 -------------------- 11 For each opp entry in 'operating-points-v2' table: 12 - opp-supported-hw: Two bitmaps indicating: 13 - Supported speed grade mask 14 - Supported market segment mask 21 -------- 24 compatible = "operating-points-v2"; 25 opp-1000000000 { [all …]
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D | cpufreq-st.txt | 5 from the SoC, then supplies the OPP framework with 'prop' and 'supported 10 ---------------------- 16 - operating-points : [See: ../power/opp-v1.yaml] 19 -------------- 24 operating-points = <1500000 0 32 -------------------------------------------- 38 - operating-points-v2 : [See ../power/opp-v2.yaml] 41 ---------------- 45 operating-points-v2 = <&cpu0_opp_table>; 50 compatible = "operating-points-v2"; [all …]
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D | nvidia,tegra20-cpufreq.txt | 5 - clocks: Must contain an entry for the CPU clock. 6 See ../clocks/clock-bindings.txt for details. 7 - operating-points-v2: See ../bindings/opp/opp-v2.yaml for details. 8 - #cooling-cells: Should be 2. See ../thermal/thermal-cooling-devices.yaml for details. 10 For each opp entry in 'operating-points-v2' table: 11 - opp-supported-hw: Two bitfields indicating: 21 matches, the OPP gets enabled. 23 - opp-microvolt: CPU voltage triplet. 26 - cpu-supply: Phandle to the CPU power supply. 31 regulator-name = "vdd_cpu"; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/ti/ |
D | k3-am625.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR MIT 7 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 10 /dts-v1/; 12 #include "k3-am62.dtsi" 16 #address-cells = <1>; 17 #size-cells = <0>; 19 cpu-map { 40 compatible = "arm,cortex-a53"; 43 enable-method = "psci"; 44 i-cache-size = <0x8000>; [all …]
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | omap34xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/media/omap3-isp.h> 16 /* OMAP343x/OMAP35xx variants OPP1-6 */ 17 operating-points-v2 = <&cpu0_opp_table>; 19 clock-latency = <300000>; /* From legacy driver */ 20 #cooling-cells = <2>; 24 cpu0_opp_table: opp-table { 25 compatible = "operating-points-v2-ti-cpu"; [all …]
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D | am33xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/pinctrl/am33xx.h> 11 #include <dt-bindings/clock/am3.h> 15 interrupt-parent = <&intc>; 16 #address-cells = <1>; 17 #size-cells = <1>; 30 d-can0 = &dcan0; [all …]
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D | omap36xx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ 8 #include <dt-bindings/bus/ti-sysc.h> 9 #include <dt-bindings/media/omap3-isp.h> 21 operating-points-v2 = <&cpu0_opp_table>; 23 vbb-supply = <&abb_mpu_iva>; 24 clock-latency = <300000>; /* From omap-cpufreq driver */ 25 #cooling-cells = <2>; 29 cpu0_opp_table: opp-table { 30 compatible = "operating-points-v2-ti-cpu"; [all …]
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/linux-6.12.1/drivers/cpufreq/ |
D | sun50i-cpufreq-nvmem.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * The sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to 6 * provide the OPP framework with required information. 13 #include <linux/arm-smccc.h> 16 #include <linux/nvmem-consumer.h> 39 * the slowest bin. Expected efuse values are 1-3, slowest in sun50i_h6_efuse_xlate() 43 return efuse_value - 1; in sun50i_h6_efuse_xlate() 58 * Judging by the OPP tables in the vendor BSP, the quality order of the 59 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best. 60 * 0 and 2 seem identical from the OPP tables' point of view. [all …]
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/linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
D | mt8188.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include <dt-bindings/clock/mediatek,mt8188-clk.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> 14 #include <dt-bindings/power/mediatek,mt8188-power.h> 15 #include <dt-bindings/reset/mt8188-resets.h> [all …]
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D | mt8186.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com> 6 /dts-v1/; 7 #include <dt-bindings/clock/mt8186-clk.h> 8 #include <dt-bindings/gce/mt8186-gce.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/memory/mt8186-memory-port.h> 12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h> 13 #include <dt-bindings/power/mt8186-power.h> [all …]
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