Searched +full:opp +full:- +full:shared (Results 1 – 25 of 189) sorted by relevance
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/linux-6.12.1/Documentation/devicetree/bindings/opp/ |
D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 - $ref: opp-v2-base.yaml# 17 const: operating-points-v2 22 - | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states [all …]
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D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Allwinner H6 CPU OPP 10 - Chen-Yu Tsai <wens@csie.org> 11 - Maxime Ripard <mripard@kernel.org> 15 OPP varies based on the silicon variant in use. Allwinner Process 20 - $ref: opp-v2-base.yaml# 25 - allwinner,sun50i-h6-operating-points [all …]
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D | opp-v2-kryo-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Technologies, Inc. NVMEM OPP 10 - Ilia Lin <ilia.lin@kernel.org> 13 - $ref: opp-v2-base.yaml# 17 the CPU frequencies subset and voltage value of each OPP varies based on 22 The qcom-cpufreq-nvmem driver reads the efuse value from the SoC to provide 23 the OPP framework with required information (existing HW bitmap). [all …]
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D | opp-v2-base.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Generic OPP (Operating Performance Points) Common Properties 10 - Viresh Kumar <viresh.kumar@linaro.org> 13 Devices work at voltage-current-frequency combinations and some implementations 25 pattern: '^opp-table(-[a-z0-9]+)?$' 27 opp-shared: 29 Indicates that device nodes using this OPP Table Node's phandle switch [all …]
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D | operating-points-v2-ti-cpu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/opp/operating-points-v2-ti-cpu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: TI CPU OPP (Operating Performance Points) 12 OPP vary based on the silicon variant used. The data sheet sections 18 This document extends the operating-points-v2 binding by providing 22 - Dhruva Gole <d-gole@ti.com> 25 - $ref: opp-v2-base.yaml# 29 const: operating-points-v2-ti-cpu [all …]
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
D | rk3588j.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "rk3588-extra.dtsi" 10 cluster0_opp_table: opp-table-cluster0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 14 opp-1416000000 { 15 opp-hz = /bits/ 64 <1416000000>; 16 opp-microvolt = <750000 750000 950000>; 17 clock-latency-ns = <40000>; 18 opp-suspend; [all …]
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D | rk3588-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 4 cluster0_opp_table: opp-table-cluster0 { 5 compatible = "operating-points-v2"; 6 opp-shared; 8 opp-1008000000 { 9 opp-hz = /bits/ 64 <1008000000>; 10 opp-microvolt = <675000 675000 950000>; 11 clock-latency-ns = <40000>; 13 opp-1200000000 { 14 opp-hz = /bits/ 64 <1200000000>; [all …]
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D | rk3399-t.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 7 #include "rk3399-base.dtsi" 10 cluster0_opp: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 15 opp-hz = /bits/ 64 <408000000>; 16 opp-microvolt = <875000 875000 1250000>; 17 clock-latency-ns = <40000>; 20 opp-hz = /bits/ 64 <600000000>; [all …]
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D | rk3399.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 6 #include "rk3399-base.dtsi" 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <825000 825000 1250000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; [all …]
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D | rk3399-op1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd 9 cluster0_opp: opp-table-0 { 10 compatible = "operating-points-v2"; 11 opp-shared; 14 opp-hz = /bits/ 64 <408000000>; 15 opp-microvolt = <800000>; 16 clock-latency-ns = <40000>; 19 opp-hz = /bits/ 64 <600000000>; 20 opp-microvolt = <825000>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/amlogic/ |
D | meson-g12b-s922x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "meson-g12b.dtsi" 10 cpu_opp_table_0: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 14 opp-1000000000 { 15 opp-hz = /bits/ 64 <1000000000>; 16 opp-microvolt = <731000>; 19 opp-1200000000 { 20 opp-hz = /bits/ 64 <1200000000>; [all …]
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D | meson-g12b-a311d.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "meson-g12b.dtsi" 10 cpu_opp_table_0: opp-table-0 { 11 compatible = "operating-points-v2"; 12 opp-shared; 14 opp-1000000000 { 15 opp-hz = /bits/ 64 <1000000000>; 16 opp-microvolt = <761000>; 19 opp-1200000000 { 20 opp-hz = /bits/ 64 <1200000000>; [all …]
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/linux-6.12.1/arch/arm/boot/dts/samsung/ |
D | exynos4210.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 7 * Copyright (c) 2010-2011 Linaro Ltd. 20 #include "exynos4-cpu-thermal.dtsi" 31 bus_acp: bus-acp { 32 compatible = "samsung,exynos-bus"; 34 clock-names = "bus"; 35 operating-points-v2 = <&bus_acp_opp_table>; 38 bus_acp_opp_table: opp-table { 39 compatible = "operating-points-v2"; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/cpufreq/ |
D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names. 6 - clock-names: Should contain the following: 7 "cpu" - The multiplexer for clock input of CPU cluster. 8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock 11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for 13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml 15 - proc-supply: Regulator for Vproc of CPU cluster. 18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver 23 - mediatek,cci: 30 - #cooling-cells: [all …]
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D | apple,cluster-cpufreq.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Hector Martin <marcan@marcan.st> 13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of 15 operating-points-v2 table to define the CPU performance states, with the 16 opp-level property specifying the hardware p-state index for that level. 21 - items: 22 - enum: [all …]
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/linux-6.12.1/arch/arm64/boot/dts/exynos/ |
D | exynos5433-bus.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 11 compatible = "samsung,exynos-bus"; 13 clock-names = "bus"; 14 operating-points-v2 = <&bus_g2d_400_opp_table>; 19 compatible = "samsung,exynos-bus"; 21 clock-names = "bus"; 22 operating-points-v2 = <&bus_g2d_266_opp_table>; 27 compatible = "samsung,exynos-bus"; 29 clock-names = "bus"; 30 operating-points-v2 = <&bus_gscl_opp_table>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/qcom/ |
D | sa8540p.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause 9 /delete-node/ &cpu0_opp_table; 10 /delete-node/ &cpu4_opp_table; 13 cpu0_opp_table: opp-table-cpu0 { 14 compatible = "operating-points-v2"; 15 opp-shared; 17 opp-300000000 { 18 opp-hz = /bits/ 64 <300000000>; 19 opp-peak-kBps = <(300000 * 32)>; 21 opp-403200000 { [all …]
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/linux-6.12.1/arch/arm/boot/dts/rockchip/ |
D | rk3229.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 11 /delete-node/ opp-table0; 13 cpu0_opp_table: opp-table-0 { 14 compatible = "operating-points-v2"; 15 opp-shared; 17 opp-408000000 { 18 opp-hz = /bits/ 64 <408000000>; 19 opp-microvolt = <950000>; 20 clock-latency-ns = <40000>; 21 opp-suspend; [all …]
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/linux-6.12.1/arch/arm/boot/dts/allwinner/ |
D | sun8i-r40-cpu-opp.dtsi | 2 cpu0_opp_table: opp-table-cpu { 3 compatible = "operating-points-v2"; 4 opp-shared; 6 opp-720000000 { 7 opp-hz = /bits/ 64 <720000000>; 8 opp-microvolt = <1000000 1000000 1300000>; 9 clock-latency-ns = <2000000>; 12 opp-912000000 { 13 opp-hz = /bits/ 64 <912000000>; 14 opp-microvolt = <1100000 1100000 1300000>; [all …]
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/linux-6.12.1/drivers/opp/ |
D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Generic OPP helper interface for CPU device 5 * Copyright (C) 2009-2014 Texas Instruments Incorporated. 20 #include "opp.h" 25 * dev_pm_opp_init_cpufreq_table() - create a cpufreq table for a device 29 * Generate a cpufreq table for a provided device- this assumes that the 30 * opp table is already initialized and ready for usage. 36 * Returns -EINVAL for bad pointers, -ENODEV if the device is not found, -ENOMEM 46 struct dev_pm_opp *opp; in dev_pm_opp_init_cpufreq_table() local 53 return max_opps ? max_opps : -ENODATA; in dev_pm_opp_init_cpufreq_table() [all …]
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D | opp.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Generic OPP Interface 5 * Copyright (C) 2009-2010 Texas Instruments Incorporated. 26 /* Lock to allow exclusive modification to the device and opp lists */ 31 /* OPP Config flags */ 41 * struct opp_config_data - data for set config operations 42 * @opp_table: OPP table 43 * @flags: OPP config flags 45 * This structure stores the OPP config information for each OPP table 54 * struct dev_pm_opp_icc_bw - Interconnect bandwidth values [all …]
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/linux-6.12.1/arch/arm/boot/dts/sigmastar/ |
D | mstar-infinity.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #include "mstar-v7.dtsi" 9 #include <dt-bindings/gpio/msc313-gpio.h> 13 compatible = "operating-points-v2"; 14 opp-shared; 16 opp-240000000 { 17 opp-hz = /bits/ 64 <240000000>; 18 opp-microvolt = <1000000>; 19 clock-latency-ns = <300000>; 22 opp-400000000 { [all …]
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/linux-6.12.1/arch/arm64/boot/dts/allwinner/ |
D | sun50i-a64-cpu-opp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 7 cpu0_opp_table: opp-table-cpu { 8 compatible = "operating-points-v2"; 9 opp-shared; 11 opp-648000000 { 12 opp-hz = /bits/ 64 <648000000>; 13 opp-microvolt = <1040000>; 14 clock-latency-ns = <244144>; /* 8 32k periods */ 17 opp-816000000 { 18 opp-hz = /bits/ 64 <816000000>; [all …]
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D | sun50i-h5-cpu-opp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 // Copyright (C) 2020 Chen-Yu Tsai <wens@csie.org> 5 cpu_opp_table: opp-table-cpu { 6 compatible = "operating-points-v2"; 7 opp-shared; 9 opp-408000000 { 10 opp-hz = /bits/ 64 <408000000>; 11 opp-microvolt = <1000000 1000000 1310000>; 12 clock-latency-ns = <244144>; /* 8 32k periods */ 15 opp-648000000 { [all …]
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/linux-6.12.1/drivers/cpufreq/ |
D | scmi-cpufreq.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2018-2021 ARM Ltd. 11 #include <linux/clk-provider.h> 38 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_get_rate() 42 ret = perf_ops->freq_get(ph, priv->domain_id, &rate, false); in scmi_cpufreq_get_rate() 49 * perf_ops->freq_set is not a synchronous, the actual OPP change will 56 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_set_target() 57 u64 freq = policy->freq_table[index].frequency; in scmi_cpufreq_set_target() 59 return perf_ops->freq_set(ph, priv->domain_id, freq * 1000, false); in scmi_cpufreq_set_target() 65 struct scmi_data *priv = policy->driver_data; in scmi_cpufreq_fast_switch() [all …]
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