Searched +full:nwl +full:- +full:pcie +full:- +full:2 (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Xilinx NWL PCIe Root Port Bridge10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com>13 - $ref: /schemas/pci/pci-host-bridge.yaml#14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#18 const: xlnx,nwl-pcie-2.1122 - description: PCIe bridge registers location.[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * PCIe host controller driver for NWL PCIe Bridge4 * Based on pcie-xilinx.c, pci-tegra.c6 * (C) Copyright 2014 - 2015, Xilinx, Inc.21 #include <linux/pci-ecam.h>34 /* Egress - Bridge translation registers */44 /* Ingress - address translations */52 /* Rxed msg fifo - Interrupt status registers */64 #define CFG_ENABLE_INT_MSG_FWD BIT(2)106 #define MSGF_LEG_SR_INTC BIT(2)[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * (C) Copyright 2014 - 2021, Xilinx, Inc.11 * published by the Free Software Foundation; either version 2 of15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>16 #include <dt-bindings/gpio/gpio.h>17 #include <dt-bindings/interrupt-controller/arm-gic.h>18 #include <dt-bindings/interrupt-controller/irq.h>19 #include <dt-bindings/power/xlnx-zynqmp-power.h>20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>24 #address-cells = <2>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>7 #include <dt-bindings/clock/imx8mq-clock.h>8 #include <dt-bindings/power/imx8mq-power.h>9 #include <dt-bindings/reset/imx8mq-reset.h>10 #include <dt-bindings/gpio/gpio.h>11 #include "dt-bindings/input/input.h"12 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #include <dt-bindings/thermal/thermal.h>14 #include <dt-bindings/interconnect/imx8mq.h>[all …]