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/linux-6.12.1/Documentation/devicetree/bindings/mailbox/
Dti,omap-mailbox.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
26 interrupt configuration registers, and have a rx and tx interrupt source per
28 appropriate programming of the rx and tx interrupt sources on the appropriate
31 The number of h/w fifo queues and interrupt lines dictate the usable
34 h/w fifo queues and interrupt lines between different instances. The interrupt
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dbrcm,systemport.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
15 - brcm,systemport-v1.00
16 - brcm,systemportlite-v1.00
17 - brcm,systemport
25 - description: interrupt line for RX queues
26 - description: interrupt line for TX queues
27 - description: interrupt line for Wake-on-LAN
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Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
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/linux-6.12.1/drivers/net/wireless/intel/iwlwifi/fw/api/
Dtx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation
4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_tx_flags - bitmasks for tx_flags in TX command
12 * @TX_CMD_FLG_PROT_REQUIRE: use RTS or CTS-to-self to protect the frame
13 * @TX_CMD_FLG_WRITE_TX_POWER: update current tx power value in the mgmt frame
15 * @TX_CMD_FLG_STA_RATE: use RS table with initial index from the TX command.
16 * Otherwise, use rate_n_flags from the TX command
28 * Should be set for mgmt, non-QOS data, mcast, bcast and in scan command
29 * @TX_CMD_FLG_MORE_FRAG: this frame is non-last MPDU
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Dmac.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022, 2024 Intel Corporation
11 * AUX indices follows - 1 for non-CDB, 2 for CDB.
31 * enum iwl_mac_protection_flags - MAC context flags
50 * enum iwl_mac_types - Supported MAC types
54 * @FW_MAC_TYPE_PIBSS: Pseudo-IBSS
78 * enum iwl_tsf_id - TSF hw timer ID
94 * struct iwl_mac_data_ap - configuration data for AP MAC context
117 * struct iwl_mac_data_ibss - configuration data for IBSS MAC context
133 * enum iwl_mac_data_policy - policy of the data path for this MAC
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/linux-6.12.1/Documentation/netlink/specs/
Drt_link.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 name: rt-link
4 protocol: netlink-raw
11 -
12 name: ifinfo-flags
15 -
17 -
19 -
21 -
23 -
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/linux-6.12.1/drivers/net/ethernet/intel/idpf/
Didpf_controlq_setup.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * idpf_ctlq_alloc_desc_ring - Allocate Control Queue (CQ) rings
14 size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc); in idpf_ctlq_alloc_desc_ring()
16 cq->desc_ring.va = idpf_alloc_dma_mem(hw, &cq->desc_ring, size); in idpf_ctlq_alloc_desc_ring()
17 if (!cq->desc_ring.va) in idpf_ctlq_alloc_desc_ring()
18 return -ENOMEM; in idpf_ctlq_alloc_desc_ring()
24 * idpf_ctlq_alloc_bufs - Allocate Control Queue (CQ) buffers
28 * Allocate the buffer head for all control queues, and if it's a receive
36 /* Do not allocate DMA buffers for transmit queues */ in idpf_ctlq_alloc_bufs()
37 if (cq->cq_type == IDPF_CTLQ_TYPE_MAILBOX_TX) in idpf_ctlq_alloc_bufs()
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/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
16 clock-names = "sata", "pmalive", "rxoob";
19 phy-names = "sata-phy";
20 ports-implemented = <0x1>;
21 power-domains = <&power RK3568_PD_PIPE>;
26 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
31 compatible = "rockchip,rk3568-qos", "syscon";
36 compatible = "rockchip,rk3568-qos", "syscon";
41 compatible = "rockchip,rk3568-qos", "syscon";
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Drk3588-extra.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk3588-base.dtsi"
7 #include "rk3588-extra-pinctrl.dtsi"
11 compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
16 clock-names = "ref_clk", "suspend_clk", "bus_clk";
19 phy-names = "usb2-phy", "usb3-phy";
21 power-domains = <&power RK3588_PD_USB>;
24 snps,dis-u2-freeclk-exists-quirk;
25 snps,dis-del-phy-power-chg-quirk;
26 snps,dis-tx-ipgap-linecheck-quirk;
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/linux-6.12.1/arch/arm/boot/dts/axis/
Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
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/linux-6.12.1/drivers/crypto/caam/
Ddpseci.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2013-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2018 NXP
21 * Maximum number of Tx/Rx queues per DPSECI object
26 * All queues considered; see dpseci_set_rx_queue()
28 #define DPSECI_ALL_QUEUES (u8)(-1)
41 * struct dpseci_cfg - Structure representing DPSECI configuration
44 * @num_tx_queues: num of queues towards the SEC
45 * @num_rx_queues: num of queues back from the SEC
47 * each place in the array is the priority of the tx queue
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/linux-6.12.1/drivers/net/ethernet/amazon/ena/
Dena_netdev.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
60 #define ENA_DEFAULT_RX_COPYBREAK (256 - NET_IP_ALIGN)
72 /* The number of tx packet completions that will be handled each NAPI poll
83 /* Number of queues to check for missing queues per timer service */
88 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
90 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1))
92 (((idx) + (n)) & ((ring_size) - 1))
97 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2)
136 * the xdp queues
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Dena_netdev.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
3 * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
56 if (txqueue >= adapter->num_io_queues) { in ena_tx_timeout()
57 netdev_err(dev, "TX timeout on invalid queue %u\n", txqueue); in ena_tx_timeout()
61 threshold = jiffies_to_usecs(dev->watchdog_timeo); in ena_tx_timeout()
62 tx_ring = &adapter->tx_ring[txqueue]; in ena_tx_timeout()
64 time_since_last_napi = jiffies_to_usecs(jiffies - tx_ring->tx_stats.last_napi_jiffies); in ena_tx_timeout()
65 napi_scheduled = !!(tx_ring->napi->state & NAPIF_STATE_SCHED); in ena_tx_timeout()
68 …"TX q %d is paused for too long (threshold %u). Time since last napi %u usec. napi scheduled: %d\n… in ena_tx_timeout()
83 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) in ena_tx_timeout()
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/linux-6.12.1/drivers/net/ethernet/intel/i40e/
Di40e_virtchnl_pf.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
55 * These variables are used to store indices, id's and number of queues
57 * termed as channel and each channel can in-turn have 4 queues which
58 * means max 16 queues overall per VF.
86 /* VSI indices - actual VSI pointers are maintained in the PF structure
87 * When assigned, these will be non-zero, because VSI 0 is always
93 u8 num_queue_pairs; /* num of qps assigned to VF vsis */
94 u8 num_req_queues; /* num of requested qps */
95 u64 num_mdd_events; /* num of mdd events detected */
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Di40e.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2021 Intel Corporation. */
29 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
38 (test_bit(I40E_HW_CAP_RSS_AQ, (pf)->hw.caps) ? 4 : 1)
42 (test_bit(I40E_HW_CAP_128_QP_RSS, (pf)->hw.caps) ? 128 : 64)
69 (&(((union i40e_rx_desc *)((R)->desc))[i]))
71 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
73 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
75 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
181 * - LINK_DOWN_ON_CLOSE_ENA is configurable at host OS run-time and
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
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/linux-6.12.1/drivers/net/ethernet/cavium/liquidio/
Docteon_config.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
25 /*--------------------------CONFIG VALUES------------------------*/
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
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Docteon_device.c7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
80 /* Num of desc for rx rings */
83 /* Num of desc for tx rings */
109 /* Num of desc for rx rings */
112 /* Num of desc for tx rings */
188 /* Num of desc for rx rings */
191 /* Num of desc for tx rings */
217 /* Num of desc for rx rings */
220 /* Num of desc for tx rings */
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/linux-6.12.1/Documentation/networking/device_drivers/ethernet/ti/
Dcpsw.rst1 .. SPDX-License-Identifier: GPL-2.0
26 - TX queues must be rated starting from txq0 that has highest priority
27 - Traffic classes are used starting from 0, that has highest priority
28 - CBS shapers should be used with rated queues
29 - The bandwidth for CBS shapers has to be set a little bit more then
30 potential incoming rate, thus, rate of all incoming tx queues has
32 - Real rates can differ, due to discreetness
33 - Map skb-priority to txq is not enough, also skb-priority to l2 prio
35 - Any l2/socket prio (0 - 7) for classes can be used, but for
37 - only 2 classes tested: A and B, but checked and can work with more,
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/linux-6.12.1/drivers/net/ethernet/broadcom/genet/
Dbcmgenet.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2024 Broadcom
23 #include <linux/dma-mapping.h>
44 /* Maximum number of hardware queues, downsized if needed */
51 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
53 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
58 /* Tx/Rx DMA register offset, skip 256 descriptors */
59 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
62 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
65 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
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/linux-6.12.1/include/xen/interface/io/
Dnetif.h1 /* SPDX-License-Identifier: MIT */
5 * Unified network-device I/O interface for Xen guest OSes.
7 * Copyright (c) 2003-2004, Keir Fraser
38 * feature 'feature-rx-notify' via xenbus. Otherwise the backend will assume
43 * "feature-split-event-channels" is introduced to separate guest TX
48 * channels for TX and RX, advertise them to backend as
49 * "event-channel-tx" and "event-channel-rx" respectively. If frontend
50 * doesn't want to use this feature, it just writes "event-channel"
55 * Multiple transmit and receive queues:
56 * If supported, the backend will write the key "multi-queue-max-queues" to
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/linux-6.12.1/drivers/dma/amd/qdma/
Dqdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * DMA driver for AMD Queue-based DMA Subsystem
5 * Copyright (C) 2023-2024, Advanced Micro Devices, Inc.
12 #include <linux/dma-map-ops.h>
19 #define CHAN_STR(q) (((q)->dir == DMA_MEM_TO_DEV) ? "H2C" : "C2H")
20 #define QDMA_REG_OFF(d, r) ((d)->roffs[r].off)
43 idx = qdev->qintr_rings[qdev->qintr_ring_idx++].ridx; in qdma_get_intr_ring_idx()
44 qdev->qintr_ring_idx %= qdev->qintr_ring_num; in qdma_get_intr_ring_idx()
52 const struct qdma_reg_field *f = &qdev->rfields[field]; in qdma_get_field()
56 low_pos = f->lsb / BITS_PER_TYPE(*data); in qdma_get_field()
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/linux-6.12.1/drivers/net/ethernet/hisilicon/hns/
Dhnae.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2014-2015 Hisilicon Limited.
11 * a set of queues provided by AE
13 * the channel between upper layer and the AE, can do tx and rx
15 * a tx or rx channel within a rbq
21 * "num" means a static number set as a parameter, "count" mean a dynamic
68 /* some said the RX and TX RCB format should not be the same in the future. But
79 #define RCB_REG_OFFSET 0x24 /* pkt num to be handled */
194 } tx; member
231 /* hnae_ring->flags fields */
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/linux-6.12.1/drivers/net/ethernet/intel/ice/
Dice.h1 /* SPDX-License-Identifier: GPL-2.0 */
19 #include <linux/dma-mapping.h>
112 #define ICE_MAX_RXQS_PER_TC 256 /* Used when setting VSI context per TC Rx queues */
122 #define ICE_MAX_MTU (ICE_AQ_SET_MAC_FRAME_SIZE_MAX - ICE_ETH_PKT_HDR_PAD)
130 #define ICE_TX_DESC(R, i) (&(((struct ice_tx_desc *)((R)->desc))[i]))
131 #define ICE_RX_DESC(R, i) (&(((union ice_32b_rx_flex_desc *)((R)->desc))[i]))
132 #define ICE_TX_CTX_DESC(R, i) (&(((struct ice_tx_ctx_desc *)((R)->desc))[i]))
133 #define ICE_TX_FDIRDESC(R, i) (&(((struct ice_fltr_desc *)((R)->desc))[i]))
159 for ((i) = 0; (i) < (pf)->num_alloc_vsi; (i)++)
161 /* Macros for each Tx/Xdp/Rx ring in a VSI */
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/linux-6.12.1/drivers/net/ethernet/google/gve/
Dgve.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 * Copyright (C) 2015-2024 Google LLC
10 #include <linux/dma-mapping.h>
32 /* 1 for management, 1 for rx, 1 for tx */
35 /* Numbers of gve tx/rx stats in stats report. */
42 /* Numbers of NIC tx/rx stats in stats report. */
48 #define GVE_DATA_SLOT_ADDR_PAGE_MASK (~(PAGE_SIZE - 1))
66 (GVE_ADMINQ_BUFFER_SIZE / sizeof(((struct gve_adminq_queried_flow_rule *)0)->location))
81 /* 2K buffers for DQO-QPL */
87 * allocs and uses a non-qpl page on the receive path of DQO QPL to free
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