/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ |
D | ti,gpmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Tony Lindgren <tony@atomide.com> 11 - Roger Quadros <rogerq@kernel.org> 16 - Asynchronous SRAM-like memories and ASICs 17 - Asynchronous, synchronous, and page mode burst NOR flash 18 - NAND flash 19 - Pseudo-SRAM devices [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/spi/ |
D | fsl,dspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 15 - enum: 16 - fsl,vf610-dspi 17 - fsl,ls1021a-v1.0-dspi 18 - fsl,ls1012a-dspi 19 - fsl,ls1028a-dspi 20 - fsl,ls1043a-dspi [all …]
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D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi", 5 "intel,lgm-spi" 6 - #address-cells: see spi-bus.txt 7 - #size-cells: see spi-bus.txt 8 - reg: address and length of the spi master registers 9 - interrupts: 10 For compatible "intel,lgm-ssc" - the common interrupt number for 18 - clocks: spi clock phandle 19 - num-cs: see spi-bus.txt, set to 8 if unset 20 - base-cs: the number of the first chip select, set to 1 if unset. [all …]
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D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michal Simek <michal.simek@amd.com> 13 - $ref: spi-controller.yaml# 18 - cdns,spi-r1p6 19 - xlnx,zynq-spi-r1p6 27 clock-names: 29 - const: ref_clk [all …]
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D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SPI-GPIO 10 - Rob Herring <robh@kernel.org> 13 This represents a group of 3-n GPIO lines used for bit-banged SPI on 17 - $ref: /schemas/spi/spi-controller.yaml# 21 const: spi-gpio 23 sck-gpios: [all …]
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D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf 5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf 6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf 9 - #address-cells: number of cells required to define a chip select 11 - #size-cells: should be zero. 12 - compatible: 13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family 14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family 15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC 17 - reg: Offset and length of SPI controller register space [all …]
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D | microchip,mpfs-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - Conor Dooley <conor.dooley@microchip.com> 19 - items: 20 - enum: 21 - microchip,mpfs-qspi 22 - microchip,pic64gx-qspi 23 - const: microchip,coreqspi-rtl-v2 [all …]
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D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Guo <shawnguo@kernel.org> 11 - Sascha Hauer <s.hauer@pengutronix.de> 12 - Fabio Estevam <festevam@gmail.com> 15 - $ref: /schemas/spi/spi-controller.yaml# 20 - enum: 21 - fsl,imx7ulp-spi [all …]
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D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzk@kernel.org> 19 - enum: 20 - google,gs101-spi 21 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 22 - samsung,s3c6410-spi 23 - samsung,s5pv210-spi # for S5PV210 and S5PC110 24 - samsung,exynos4210-spi [all …]
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D | fsl-spi.txt | 4 - cell-index : QE SPI subblock index. 7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". 8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe". 9 - reg : Offset and length of the register set for the device 10 - interrupts : <a b> where a is the interrupt number and b is a 15 - clock-frequency : input clock frequency to non FSL_SOC cores 18 - cs-gpios : specifies the gpio pins to be used for chipselects. 21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the 24 the cs-gpios property is not present. 28 cell-index = <0>; [all …]
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D | marvell,armada-3700-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/marvell,armada-3700-spi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 13 - Kousik Sanagavarapu <five231003@gmail.com> 16 - $ref: spi-controller.yaml# 20 const: marvell,armada-3700-spi 31 num-cs: 35 - compatible 36 - reg [all …]
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D | socionext,f-ospi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 17 - $ref: spi-controller.yaml# 21 const: socionext,f-ospi 29 num-cs: 34 - compatible 35 - reg [all …]
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/linux-6.12.1/drivers/net/ethernet/pasemi/ |
D | pasemi_mac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 5 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and 78 struct pasemi_mac_csring *cs[MAX_CS]; member 94 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) argument 95 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) argument 96 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) argument 97 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) argument 98 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) argument 99 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) argument 101 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \ [all …]
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/linux-6.12.1/fs/fuse/ |
D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu> 42 * Lockless access is OK, because file->private data is set in fuse_get_dev() 45 return READ_ONCE(file->private_data); in fuse_get_dev() 50 INIT_LIST_HEAD(&req->list); in fuse_request_init() 51 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init() 52 init_waitqueue_head(&req->waitq); in fuse_request_init() 53 refcount_set(&req->count, 1); in fuse_request_init() 54 __set_bit(FR_PENDING, &req->flags); in fuse_request_init() 55 req->fm = fm; in fuse_request_init() 74 refcount_inc(&req->count); in __fuse_get_request() [all …]
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/linux-6.12.1/drivers/i2c/busses/ |
D | i2c-synquacer.c | 1 // SPDX-License-Identifier: GPL-2.0 31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS 70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2) 73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3) 76 /* calculate the value of CS bits in CCR register on standard mode */ 78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \ 81 /* calculate the value of CS bits in CSR register on standard mode */ 84 /* calculate the value of CS bits in CCR register on fast mode */ 86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \ 89 /* calculate the value of CS bits in CSR register on fast mode */ [all …]
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/linux-6.12.1/arch/riscv/boot/dts/canaan/ |
D | canaan_kd233.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210"; 24 stdout-path = "serial0:115200n8"; 27 gpio-leds { 28 compatible = "gpio-leds"; 39 gpio-keys { [all …]
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D | sipeed_maix_bit.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 17 compatible = "sipeed,maix-bit", "sipeed,maix-bitm", 18 "canaan,kendryte-k210"; 26 stdout-path = "serial0:115200n8"; 29 gpio-leds { [all …]
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D | sipeed_maix_dock.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 17 compatible = "sipeed,maix-dock-m1", "sipeed,maix-dock-m1w", 18 "canaan,kendryte-k210"; 26 stdout-path = "serial0:115200n8"; 29 gpio-leds { [all …]
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D | sipeed_maixduino.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 16 compatible = "sipeed,maixduino", "canaan,kendryte-k210"; 24 stdout-path = "serial0:115200n8"; 27 gpio-keys { 28 compatible = "gpio-keys"; 30 key-boot { [all …]
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D | sipeed_maix_go.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 7 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/leds/common.h> 17 compatible = "sipeed,maix-go", "canaan,kendryte-k210"; 25 stdout-path = "serial0:115200n8"; 28 gpio-leds { 29 compatible = "gpio-leds"; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/toshiba/ |
D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 10 #include <dt-bindings/clock/toshiba,tmpv770x.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; 23 #size-cells = <0>; [all …]
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/linux-6.12.1/drivers/net/ethernet/cavium/liquidio/ |
D | octeon_device.c | 7 * Copyright (c) 2003-2016 Cavium, Inc. 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 80 /* Num of desc for rx rings */ 83 /* Num of desc for tx rings */ 109 /* Num of desc for rx rings */ 112 /* Num of desc for tx rings */ 188 /* Num of desc for rx rings */ 191 /* Num of desc for tx rings */ 217 /* Num of desc for rx rings */ 220 /* Num of desc for tx rings */ [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver === 17 * compatible: should be defined as "st,spear-spics-gpio" 19 * st-spics,peripcfg-reg: peripheral configuration register offset 20 * st-spics,sw-enable-bit: bit offset to enable sw control 21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high 22 * st-spics,cs-enable-mask: chip select number bit mask 23 * st-spics,cs-enable-shift: chip select number program offset 24 * gpio-controller: Marks the device node as gpio controller 25 * #gpio-cells: should be 1 and will mention chip select number 30 ------- [all …]
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/linux-6.12.1/arch/arm/boot/dts/hisilicon/ |
D | hi3519.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <dt-bindings/clock/hi3519-clock.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #address-cells = <1>; 10 #size-cells = <1>; 14 #address-cells = <1>; 15 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; 24 gic: interrupt-controller@10300000 { 25 compatible = "arm,cortex-a7-gic"; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/pci/ |
D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 13 - device_type: Must be "pci" 14 - reg: A list of physical base address and length for each set of controller 15 registers. Must contain an entry for each entry in the reg-names property. [all …]
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