/linux-6.12.1/Documentation/devicetree/bindings/pci/ |
D | v3-v360epc-pci.txt | 6 - compatible: should be one of: 7 "v3,v360epc-pci" 8 "arm,integrator-ap-pci", "v3,v360epc-pci" 9 - reg: should contain two register areas: 12 - interrupts: should contain a reference to the V3 error interrupt 14 - bus-range: see pci.txt 15 - ranges: this follows the standard PCI bindings in the IEEE Std 16 1275-1994 (see pci.txt) with the following restriction: 17 - The non-prefetchable and prefetchable memory windows must 19 - The prefetchable memory window must be immediately adjacent [all …]
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D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be: 5 - "nvidia,tegra20-pcie": for Tegra20 6 - "nvidia,tegra30-pcie": for Tegra30 7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132 8 - "nvidia,tegra210-pcie": for Tegra210 9 - "nvidia,tegra186-pcie": for Tegra186 10 - power-domains: To ungate power partition by BPMP powergate driver. Must 13 - device_type: Must be "pci" 14 - reg: A list of physical base address and length for each set of controller 15 registers. Must contain an entry for each entry in the reg-names property. [all …]
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D | versatile.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 16 - $ref: /schemas/pci/pci-host-bridge.yaml# 20 const: arm,versatile-pci 24 - description: Versatile-specific registers 25 - description: Self Config space 26 - description: Config space 31 "#interrupt-cells": true [all …]
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D | faraday,ftpci100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 21 The plain variant has 128MiB of non-prefetchable memory space, whereas the 27 and should point to respective interrupt in that controller in its interrupt-map. 29 The code which is the only documentation of how the Faraday PCI (the non-dual 34 interrupt-map-mask = <0xf800 0 0 7>; 35 interrupt-map = 54 - $ref: /schemas/pci/pci-host-bridge.yaml# [all …]
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D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Will Deacon <will@kernel.org> 13 Firmware-initialised PCI host controllers and PCI emulations, such as the 14 virtio-pci implementations found in kvmtool and other para-virtualised 21 Configuration Space is assumed to be memory-mapped (as opposed to being 26 For CAM, this 24-bit offset is: 41 - description: [all …]
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D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of 20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 26 - nvidia,tegra194-pcie [all …]
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D | pci-armada8k.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 7 - compatible: "marvell,armada8k-pcie" 8 - reg: must contain two register regions 9 - the control register region 10 - the config space region 11 - reg-names: 12 - "ctrl" for the control register region 13 - "config" for the config space region 14 - interrupts: Interrupt specifier for the PCIe controller 15 - clocks: reference to the PCIe controller clocks [all …]
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D | axis,artpec6-pcie.txt | 1 * Axis ARTPEC-6 PCIe interface 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml. 7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; 8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; 9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode; 10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode; 11 - reg: base addresses and lengths of the PCIe controller (DBI), 13 - reg-names: Must include the following entries: 14 - "dbi" 15 - "phy" [all …]
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D | fsl,layerscape-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 16 which is used to describe the PLL settings at the time of chip-reset. 26 - enum: 27 - fsl,ls1012a-pcie 28 - fsl,ls1021a-pcie 29 - fsl,ls1028a-pcie [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 5 * Copyright 2014-2016 Freescale Semiconductor, Inc. 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include "fsl-ls208xa.dtsi" 17 compatible = "arm,cortex-a57-pmu"; 25 compatible = "arm,cortex-a57"; 28 cpu-idle-states = <&CPU_PW20>; 29 next-level-cache = <&cluster0_l2>; 30 #cooling-cells = <2>; [all …]
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D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 5 * Copyright 2018-2020 NXP 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; [all …]
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/linux-6.12.1/drivers/pci/ |
D | setup-bus.c | 1 // SPDX-License-Identifier: GPL-2.0 11 * PCI-PCI bridges cleanup, sorted resource allocation. 14 * tighter packing. Prefetchable range support. 50 list_del(&dev_res->list); in free_list() 56 * add_to_list() - Add a new resource tracker to the list 71 return -ENOMEM; in add_to_list() 73 tmp->res = res; in add_to_list() 74 tmp->dev = dev; in add_to_list() 75 tmp->start = res->start; in add_to_list() 76 tmp->end = res->end; in add_to_list() [all …]
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D | setup-res.c | 1 // SPDX-License-Identifier: GPL-2.0 32 struct resource *res = dev->resource + resno; in pci_std_update_resource() 35 /* Per SR-IOV spec 3.4.1.11, VF BARs are RO zero */ in pci_std_update_resource() 36 if (dev->is_virtfn) in pci_std_update_resource() 43 if (!res->flags) in pci_std_update_resource() 46 if (res->flags & IORESOURCE_UNSET) in pci_std_update_resource() 50 * Ignore non-moveable resources. This might be legacy resources for in pci_std_update_resource() 54 if (res->flags & IORESOURCE_PCI_FIXED) in pci_std_update_resource() 57 pcibios_resource_to_bus(dev->bus, ®ion, res); in pci_std_update_resource() 60 if (res->flags & IORESOURCE_IO) { in pci_std_update_resource() [all …]
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/linux-6.12.1/drivers/pci/controller/ |
D | pci-v3-semi.c | 1 // SPDX-License-Identifier: GPL-2.0 6 * Based on the code from arch/arm/mach-integrator/pci_v3.c 8 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd 134 /* PCI BASE bits (PCI -> Local Bus) */ 141 /* PCI MAP bits (PCI -> Local bus) */ 150 /* LB_BASE0,1 bits (Local bus -> PCI) */ 172 /* LB_MAP0,1 bits (Local bus -> PCI) */ 185 /* LB_BASE2 bits (Local bus -> PCI IO) */ 192 /* LB_MAP2 bits (Local bus -> PCI IO) */ 229 /* ARM Integrator-specific extended control registers */ [all …]
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D | pci-thunder-pem.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2015 - 2016 Cavium, Inc. 12 #include <linux/pci-acpi.h> 13 #include <linux/pci-ecam.h> 15 #include <linux/io-64-nonatomic-lo-hi.h> 26 * N.B. This is a non-standard platform-specific ECAM bus shift value. For 28 * include/linux/pci-ecam.h. 41 struct pci_config_window *cfg = bus->sysdata; in thunder_pem_bridge_read() 42 struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv; in thunder_pem_bridge_read() 48 * 32-bit accesses only. Write the address to the low order in thunder_pem_bridge_read() [all …]
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/linux-6.12.1/arch/arm/boot/dts/st/ |
D | spear1310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 15 compatible = "st,spear-spics-gpio"; 17 st-spics,peripcfg-reg = <0x3b0>; 18 st-spics,sw-enable-bit = <12>; 19 st-spics,cs-value-bit = <11>; 20 st-spics,cs-enable-mask = <3>; 21 st-spics,cs-enable-shift = <8>; 22 gpio-controller; 23 #gpio-cells = <2>; 27 compatible = "st,spear1310-miphy"; [all …]
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D | spear1340.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later 16 compatible = "st,spear-spics-gpio"; 18 st-spics,peripcfg-reg = <0x42c>; 19 st-spics,sw-enable-bit = <21>; 20 st-spics,cs-value-bit = <20>; 21 st-spics,cs-enable-mask = <3>; 22 st-spics,cs-enable-shift = <18>; 23 gpio-controller; 24 #gpio-cells = <2>; 29 compatible = "st,spear1340-miphy"; [all …]
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/linux-6.12.1/arch/arm/boot/dts/arm/ |
D | versatile-pb.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "versatile-ab.dts" 6 compatible = "arm,versatile-pb"; 10 sic: interrupt-controller@10003000 { 11 clear-mask = <0xffffffff>; 14 * figure 3-30 page 3-74 of ARM DUI 0224B 16 valid-mask = <0x7fe003ff>; 23 gpio-controller; 24 #gpio-cells = <2>; 25 interrupt-controller; [all …]
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/linux-6.12.1/arch/x86/pci/ |
D | broadcom_bus.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 14 #include <asm/pci-direct.h> 45 /* read the non-prefetchable memory window */ in cnb20le_res() 55 /* read the prefetchable memory window */ in cnb20le_res() 81 list_for_each_entry(root_res, &info->resources, list) in cnb20le_res() 82 printk(KERN_INFO "host bridge window %pR\n", &root_res->res); in cnb20le_res()
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/linux-6.12.1/sound/pci/lx6464es/ |
D | lx6464es.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* -*- linux-c -*- * 65 void __iomem *port_dsp_bar; /* memory port (32-bit, 66 * non-prefetchable,
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/linux-6.12.1/arch/powerpc/boot/ |
D | cuboot-pq2.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Old U-boot compatibility for PowerQUICC II 15 #include "fsl-soc.h" 40 /* Different versions of u-boot put the BCSR in different places, and 44 * For any node defined as compatible with fsl,pq2-localbus, 58 if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus")) in update_cs_ranges() 103 option | ~(cs_ranges_buf[i].size - 1)); in update_cs_ranges() 113 /* Older u-boots don't set PCI up properly. Update the hardware to match 114 * the device tree. The prefetch mem region and non-prefetch mem region 117 * 32-bit PCI is supported. All three region types (prefetchable mem, [all …]
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/linux-6.12.1/arch/arm64/boot/dts/marvell/ |
D | armada-cp11x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include <dt-bindings/interrupt-controller/mvebu-icu.h> 9 #include <dt-bindings/thermal/thermal.h> 11 #include "armada-common.dtsi" 27 thermal-zones { 28 CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(ic-thermal) { 29 polling-delay-passive = <0>; /* Interrupt driven */ 30 polling-delay = <0>; /* Interrupt driven */ 32 thermal-sensors = <&CP11X_LABEL(thermal) 0>; 42 cooling-maps { }; [all …]
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/linux-6.12.1/arch/powerpc/platforms/powernv/ |
D | pci-sriov.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 13 * The majority of the complexity in supporting SR-IOV on PowerNV comes from 20 * the address range that we want to map to be power-of-two sized and aligned. 24 * For a SR-IOV BAR things are a little more awkward since size and alignment 25 * are not coupled. The alignment is set based on the per-VF BAR size, but 26 * the total BAR area is: number-of-vfs * per-vf-size. The number of VFs 29 * allocate the SR-IOV BARs in a way that lets us map them using the MBT. 32 * of MBT entry that we use. We only support SR-IOV on PHB3 (IODA2) and above, 40 * b) An un-segmented BAR that maps the whole address range to a specific PE. 43 * We prefer to use mode a) since it only requires one MBT entry per SR-IOV BAR [all …]
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/linux-6.12.1/Documentation/admin-guide/media/ |
D | pci-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 - Vendor ID and device ID; 10 - Subsystem ID and Subsystem device ID; 12 The ``lspci -nn`` command allows identifying the vendor/device PCI IDs: 14 .. code-block:: none 15 :emphasize-lines: 3 17 $ lspci -nn 23 …02:02.0 Multimedia video controller [0400]: Conexant Systems, Inc. CX23418 Single-Chip MPEG-2 Enco… 27 The subsystem IDs can be obtained using ``lspci -vn`` 29 .. code-block:: none [all …]
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/linux-6.12.1/include/uapi/linux/ |
D | pci_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 5 * Copyright 1997--1999 Martin Mares <mj@ucw.cz> 25 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of 26 * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of 50 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */ 59 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */ 83 #define PCI_HEADER_TYPE_MFD 0x80 /* Multi-Function Device (possible) */ 109 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */ 124 /* 0x35-0x3b are reserved */ 130 /* Header type 1 (PCI-to-PCI bridges) */ [all …]
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