| /linux-6.12.1/Documentation/admin-guide/mm/ |
| D | numa_memory_policy.rst | 10 supported platforms with Non-Uniform Memory Access architectures since 2.4.?.
16 (``Documentation/admin-guide/cgroup-v1/cpusets.rst``)
19 programming interface that a NUMA-aware application can take advantage of. When
28 ------------------------
39 up, the system default policy will be set to interleave
41 not to overload the initial boot node with boot-time
45 this is an optional, per-task policy. When defined for a
61 In a multi-threaded task, task policies apply only to the thread
98 mapping-- i.e., at Copy-On-Write.
101 virtual address space--a.k.a. threads--independent of when
[all …]
|
| D | hugetlbpage.rst | 13 256M and ppc64 supports 4K and 16M. A TLB is a cache of virtual-to-physical
93 Once a number of huge pages have been pre-allocated to the kernel huge page
169 indicates the current number of pre-allocated huge pages of the default size.
180 task that modifies ``nr_hugepages``. The default for the allowed nodes--when the
181 task has default memory policy--is all on-line nodes with memory. Allowed
206 requested by applications. Writing any non-zero value into this file
226 of the in-use huge pages to surplus huge pages. This will occur even if
228 this condition holds--that is, until ``nr_hugepages+nr_overcommit_hugepages`` is
229 increased sufficiently, or the surplus huge pages go out of use and are freed--
232 With support for multiple huge page pools at run-time available, much of
[all …]
|
| /linux-6.12.1/drivers/mtd/chips/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
[all …]
|
| D | cfi_util.c | 1 // SPDX-License-Identifier: GPL-2.0
43 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr() local
44 unsigned type = cfi->device_type; in cfi_build_cmd_addr()
47 addr = (cmd_ofs * type) * interleave; in cfi_build_cmd_addr()
54 if (((type * interleave) > bankwidth) && ((cmd_ofs & 0xff) == 0xaa)) in cfi_build_cmd_addr()
55 addr |= (type >> 1)*interleave; in cfi_build_cmd_addr()
62 * Transforms the CFI command for the given geometry (bus width & interleave).
88 /* First, determine what the bit-pattern should be for a single in cfi_build_cmd()
122 /* And finally, for the multi-word case, replicate it in cfi_build_cmd()
178 /* Last, determine what the bit-pattern should be for a single in cfi_merge_status()
[all …]
|
| D | cfi_cmdset_0020.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * - completely revamped method functions so they are aware and
10 * independent of the flash geometry (buswidth, interleave, etc.)
11 * - scalability vs code size is completely set at compile-time
13 * - optimized write buffer method
14 * 06/21/2002 Joern Engel <joern@wh.fh-wedel.de> and others
15 * - modified Intel Command Set 0x0001 to support ST Advanced Architecture
17 * - added a writev function
18 * 07/13/2005 Joern Engel <joern@wh.fh-wedel.de>
19 * - Plugged memory leak in cfi_staa_writev().
[all …]
|
| /linux-6.12.1/drivers/ras/amd/atl/ |
| D | internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
108 * interleave modes with a number of channels divisible by 3 or the
109 * value will be 5 for interleave modes with a number of channels
110 * divisible by 5. Power-of-two interleave modes are handled
118 * address. The other bits depend on the interleave bit position which
119 * will be bit 10 for 1K interleave stripe cases and bit 11 for 2K
120 * interleave stripe cases.
147 * These masks operate on the 16-bit Coherent Station IDs,
156 * Least-significant bit of Node ID portion of the
157 * system-wide Coherent Station Fabric ID.
[all …]
|
| D | reg_fields.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
216 * Hash Interleave Controls
299 * Interleave Address Select
311 * D18F7xE0C [DRAM Address Interleave]
314 * D18F7x20C [DRAM Address Interleave]
322 * Interleave Number of Channels
334 * D18F7xE0C [DRAM Address Interleave]
337 * D18F7x20C [DRAM Address Interleave]
347 * Interleave Number of Dies
361 * D18F7xE0C [DRAM Address Interleave]
[all …]
|
| D | denormalize.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 case DF2: return FIELD_GET(DF2_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
23 case DF3: return FIELD_GET(DF3_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
24 case DF3p5: return FIELD_GET(DF3p5_DST_FABRIC_ID, ctx->map.limit); in get_dst_fabric_id()
25 case DF4: return FIELD_GET(DF4_DST_FABRIC_ID, ctx->map.ctl); in get_dst_fabric_id()
26 case DF4p5: return FIELD_GET(DF4p5_DST_FABRIC_ID, ctx->map.ctl); in get_dst_fabric_id()
38 * # of interleave bits (n): 3
39 * starting interleave bit (p): 8
41 * expanded address bits: [20+n : n+p][n+p-1 : p][p-1 : 0]
46 return expand_bits(ctx->map.intlv_bit_pos, in make_space_for_coh_st_id_at_intlv_bit()
[all …]
|
| /linux-6.12.1/Documentation/driver-api/cxl/ |
| D | memory-devices.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 range across multiple devices underneath a host-bridge or interleaved
15 across host-bridges.
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
32 at which the interleave can be split. For example platform firmware may say at a
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
40 Ports. Each of those Root Ports are connected to 2-way switches with endpoints
43 # cxl list -BEMPu -b cxl_test
185 its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
[all …]
|
| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-bus-cxl | 4 Contact: linux-cxl@vger.kernel.org
14 Contact: linux-cxl@vger.kernel.org
17 Memory Device Output Payload in the CXL-2.0
24 Contact: linux-cxl@vger.kernel.org
28 Payload in the CXL-2.0 specification.
34 Contact: linux-cxl@vger.kernel.org
40 class-ids can be compared against a similar "qos_class"
42 that the endpoints map their local memory-class to a
45 side-effects that may result. First class-id is displayed.
51 Contact: linux-cxl@vger.kernel.org
[all …]
|
| /linux-6.12.1/drivers/edac/ |
| D | i5100_edac.c | 9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
13 * can not reflect this configuration so instead the chip-select
44 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
45 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
46 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
47 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
48 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
70 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
83 #define I5100_DMIR 0x15c /* DIMM Interleave Range */
[all …]
|
| D | i7300_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet
48 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0)
49 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0)
103 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/
151 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it
170 * MTRx - Memory Technology Registers
192 [22] = "Non-Redundant Fast Reset Timeout",
195 [0] = "Memory Write error on non-redundant retry or "
203 [24] = "DIMM-Spare Copy Completed",
[all …]
|
| /linux-6.12.1/include/linux/ |
| D | sysv_fs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 On Coherent FS, they are always stored in PDP-11 manner: the least
21 /* 0 is non-existent */
26 /* Xenix super-block data on disk */
41 char s_fmod; /* super-block modified flag */
42 char s_ronly; /* flag whether fs is mounted read-only */
66 /* SystemV4 super-block data on disk */
82 char s_fmod; /* super-block modified flag */
83 char s_ronly; /* flag whether fs is mounted read-only */
92 __fs32 s_state; /* file system state: 0x7c269d38-s_time means clean */
[all …]
|
| D | libnvdimm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * libnvdimm - Non-volatile-memory Devices Subsystem
5 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
53 /* region flag indicating to direct-map persistent memory by default */
107 /* v1.1 definition of the interleave-set-cookie algorithm */
109 /* v1.2 definition of the interleave-set-cookie algorithm */
154 * 'flags == 0' corresponds to an error / not-supported state.
309 return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc); in nvdimm_ctl()
|
| /linux-6.12.1/tools/perf/scripts/python/ |
| D | intel-pt-events.py | 1 # SPDX-License-Identifier: GPL-2.0
2 # intel-pt-events.py: Print Intel PT Events including Power Events and PTWRITE
3 # Copyright (c) 2017-2021, Intel Corporation.
27 '/scripts/python/Perf-Trace-Util/lib/Perf/Trace')
47 glb_cpu = -1
77 ap.add_argument("--insn-trace", action='store_true')
78 ap.add_argument("--src-trace", action='store_true')
79 ap.add_argument("--all-switch-events", action='store_true')
80 ap.add_argument("--interleave", type=int, nargs='?', const=4, default=0)
105 if glb_args.interleave:
[all …]
|
| /linux-6.12.1/drivers/scsi/esas2r/ |
| D | esas2r_targdb.c | 5 * Copyright (c) 2001-2013 ATTO Technology, Inc.
21 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
40 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
50 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_initialize()
53 t->target_state = TS_NOT_PRESENT; in esas2r_targ_db_initialize()
54 t->buffered_target_state = TS_NOT_PRESENT; in esas2r_targ_db_initialize()
55 t->new_target_state = TS_INVALID; in esas2r_targ_db_initialize()
64 for (t = a->targetdb; t < a->targetdb_end; t++) { in esas2r_targ_db_remove_all()
65 if (t->target_state != TS_PRESENT) in esas2r_targ_db_remove_all()
68 spin_lock_irqsave(&a->mem_lock, flags); in esas2r_targ_db_remove_all()
[all …]
|
| /linux-6.12.1/sound/pci/echoaudio/ |
| D | echoaudio_dsp.h | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
41 /**** Echo24: Gina24, Layla24, Mona, Mia, Mia-midi ****/
81 * These are the offsets for the memory-mapped DSP registers; the DSP base
133 #define MIDI_IN_SKIP_DATA (-1)
136 /*----------------------------------------------------------------------------
151 -Set the clock select bits in the control register to 0xe (see the #define
154 -Set double-speed mode if you want to use sample rates above 50 kHz
[all …]
|
| D | echoaudio_dsp.c | 3 Copyright Echo Digital Audio Corporation (c) 1998 - 2004
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston,
22 MA 02111-1307, USA.
26 Translation from C++ and adaptation for use in ALSA-Driver
40 command and then write a non-zero value to the Handshake field in the
50 if (chip->comm_page->handshake) { in wait_handshake()
56 dev_err(chip->card->dev, "wait_handshake(): Timeout waiting for DSP\n"); in wait_handshake()
57 return -EBUSY; in wait_handshake()
83 dev_err(chip->card->dev, "timeout on send_vector\n"); in send_vector()
84 return -EBUSY; in send_vector()
[all …]
|
| /linux-6.12.1/mm/ |
| D | mempolicy.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 * interleave Allocate memory interleaved over a set of nodes,
22 * weighted interleave
24 * a set of weights (per-node), with normal fallback if it
25 * fails. Otherwise operates the same as interleave.
26 * Example: nodeset(0,1) & weights (2,1) - 2 pages allocated
38 * but useful to set in a VMA when you have a non default
48 * The process policy is applied for most non interrupt memory allocations
122 #define MPOL_MF_WRLOCK (MPOL_MF_INTERNAL << 2) /* Write-lock walked vmas */
132 * run-time system-wide default policy => local allocation
[all …]
|
| /linux-6.12.1/Documentation/driver-api/nvdimm/ |
| D | nvdimm.rst | 2 LIBNVDIMM: Non-Volatile Devices
5 libnvdimm - kernel / libndctl - userspace helper library
18 PMEM-REGIONs, Atomic Sectors, and DAX
50 A system-physical-address range where writes are persistent. A
52 may span an interleave of several DIMMs.
55 DIMM Physical Address, is a DIMM-relative offset. With one DIMM in
56 the system there would be a 1:1 system-physical-address:DPA association.
57 Once more DIMMs are added a memory controller interleave must be
59 system-physical-address.
68 device - in this case the firmware.
[all …]
|
| /linux-6.12.1/Documentation/fb/ |
| D | api.rst | 9 ---------------
12 with frame buffer devices. In-kernel APIs between device drivers and the frame
22 ---------------
36 - FB_CAP_FOURCC
44 --------------------
46 Pixels are stored in memory in hardware-dependent formats. Applications need
58 - FB_TYPE_PACKED_PIXELS
67 - FB_TYPE_PLANES
75 - FB_TYPE_INTERLEAVED_PLANES
81 Planes are interleaved in memory. The interleave factor, defined as the
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/sound/ |
| D | fsl,qmc-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,qmc-audio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 if only one QMC channel is used by the DAI or it is working in non-interleaved
20 - $ref: dai-common.yaml#
24 const: fsl,qmc-audio
26 '#address-cells':
28 '#size-cells':
[all …]
|
| /linux-6.12.1/drivers/acpi/nfit/ |
| D | nfit.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * NVDIMM Firmware Interface Table - NFIT
5 * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
17 #define UUID_NFIT_BUS "2f10e7a4-9e91-11e4-89d3-123b93f75cba"
19 /* https://pmem.io/documents/NVDIMM_DSM_Interface-V1.6.pdf */
20 #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
21 #define UUID_INTEL_BUS "c7d8acd4-2df8-4b82-9f65-a325335af149"
23 /* https://github.com/HewlettPackard/hpe-nvm/blob/master/Documentation/ */
24 #define UUID_NFIT_DIMM_N_HPE1 "9002c334-acf3-4c0e-9642-a235f0d53bc6"
25 #define UUID_NFIT_DIMM_N_HPE2 "5008664b-b758-41a0-a03c-27c2f2d04f7e"
[all …]
|
| /linux-6.12.1/Documentation/admin-guide/device-mapper/ |
| D | dm-integrity.rst | 2 dm-integrity
5 The dm-integrity target emulates a block device that has additional
6 per-sector tags that can be used for storing integrity information.
9 writing the sector and the integrity tag must be atomic - i.e. in case of
12 To guarantee write atomicity, the dm-integrity target uses journal, it
16 The dm-integrity target can be used with the dm-crypt target - in this
17 situation the dm-crypt target creates the integrity data and passes them
18 to the dm-integrity target via bio_integrity_payload attached to the bio.
19 In this mode, the dm-crypt and dm-integrity targets provide authenticated
20 disk encryption - if the attacker modifies the encrypted device, an I/O
[all …]
|
| /linux-6.12.1/tools/perf/Documentation/ |
| D | perf-annotate.txt | 1 perf-annotate(1)
5 ----
6 perf-annotate - Read perf.data (created by perf record) and display annotated code
9 --------
11 'perf annotate' [-i <file> | --input=file] [symbol_name]
14 -----------
22 -------
23 -i::
24 --input=<file>::
27 -d::
[all …]
|