Home
last modified time | relevance | path

Searched +full:non +full:- +full:coresight (Results 1 – 25 of 57) sorted by relevance

123

/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,coresight-cti.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: ARM Coresight Cross Trigger Interface (CTI) device.
11 The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected
12 to one or more CoreSight components and/or a CPU, with CTIs interconnected in
15 not part of the CoreSight graph.
37 indicate this feature (arm,coresight-cti-v8-arch).
48 between CTI and other CoreSight components.
[all …]
Darm,coresight-static-funnel.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-funnel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Static Trace Bus Funnel
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
[all …]
Darm,coresight-static-replicator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-static-replicator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm CoreSight Static Trace Bus Replicator
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
[all …]
Darm,coresight-catu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-catu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Coresight Address Translation Unit (CATU)
10 - Mathieu Poirier <mathieu.poirier@linaro.org>
11 - Mike Leach <mike.leach@linaro.org>
12 - Leo Yan <leo.yan@linaro.org>
13 - Suzuki K Poulose <suzuki.poulose@arm.com>
16 CoreSight components are compliant with the ARM CoreSight architecture
[all …]
/linux-6.12.1/arch/arm/boot/dts/hisilicon/
Dhip04.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-2014 HiSilicon Ltd.
6 * Copyright (C) 2013-2014 Linaro Ltd.
12 /* memory bus is 64-bit */
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "hisilicon,hip04-bootwrapper";
22 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
[all …]
/linux-6.12.1/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
[all …]
Dcoresight-ect.rst1 .. SPDX-License-Identifier: GPL-2.0
4 CoreSight Embedded Cross Trigger (CTI & CTM).
11 --------------------
13 The CoreSight Cross Trigger Interface (CTI) is a hardware device that takes
21 0 C 0----------->: : +======>(other CTI channel IO)
22 0 P 0<-----------: : v
24 0000000 : CTI :<=========>*CTM*<====>: CTI :---+
25 ####### in_trigs : : (id 0-3) ***** ::::::: v
26 # ETM #----------->: : ^ #######
27 # #<-----------: : +---# ETR #
[all …]
Dcoresight.rst2 Coresight - HW Assisted Tracing on ARM
9 ------------
11 Coresight is an umbrella of technologies allowing for the debugging of ARM
24 flows through the coresight system (via ATB bus) using links that are connecting
25 the emanating source to a sink(s). Sinks serve as endpoints to the coresight
28 host without fear of filling up the onboard coresight memory buffer.
30 At typical coresight system would look like this::
38 0 CPU 0<-->: C : 0 CPU 0<-->: C : : C : @ STM @ || System ||
39 |->0000000 : T : |->0000000 : T : : T :<--->@@@@@ || Memory ||
40 | #######<-->: I : | #######<-->: I : : I : @@@<-| ||||||||||||
[all …]
/linux-6.12.1/drivers/hwtracing/coresight/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Coresight configuration
5 menuconfig CORESIGHT config
6 tristate "CoreSight Tracing Support"
13 This framework provides a kernel interface for the CoreSight debug
15 a topological view of the CoreSight components based on a DT
20 module will be called coresight.
22 if CORESIGHT
24 tristate "CoreSight Link and Sink drivers"
26 This enables support for CoreSight link and sink drivers that are
[all …]
Dcoresight-platform.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/coresight.h>
19 #include "coresight-priv.h"
24 * If the output port is already assigned on this device, return -EINVAL
37 for (i = 0; i < pdata->nr_outconns; ++i) { in coresight_add_out_conn()
38 conn = pdata->out_conns[i]; in coresight_add_out_conn()
39 /* Output == -1 means ignore the port for example for helpers */ in coresight_add_out_conn()
40 if (conn->src_port != -1 && in coresight_add_out_conn()
41 conn->src_port == new_conn->src_port) { in coresight_add_out_conn()
43 conn->src_port); in coresight_add_out_conn()
[all …]
Dcoresight-cti-platform.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/coresight.h>
12 #include <dt-bindings/arm/coresight-cti-dt.h>
14 #include "coresight-cti.h"
15 #include "coresight-priv.h"
23 #define CTI_DT_CONNS "trig-conns"
26 #define CTI_DT_V8ARCH_COMPAT "arm,coresight-cti-v8-arch"
27 #define CTI_DT_CSDEV_ASSOC "arm,cs-dev-assoc"
28 #define CTI_DT_TRIGIN_SIGS "arm,trig-in-sigs"
29 #define CTI_DT_TRIGOUT_SIGS "arm,trig-out-sigs"
[all …]
Dcoresight-etm3x-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Program Flow Trace driver
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
35 #include "coresight-trace-id.h"
57 drvdata->os_unlock = true; in etm_os_unlock()
89 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR); in etm_set_pwrup()
[all …]
Dcoresight-cpu-debug.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/coresight.h>
29 #include "coresight-priv.h"
69 * 0b0000 - Sample offset applies based on the instruction state, we
71 * 0b0001 - No offset applies.
72 * 0b0010 - No offset applies, but do not use in AArch32 mode
113 MODULE_PARM_DESC(enable, "Control to enable coresight CPU debug functionality");
118 writel_relaxed(0x0, drvdata->base + EDOSLAR); in debug_os_unlock()
130 * - CPU power domain is powered off;
131 * - The OS Double Lock is locked;
[all …]
Dcoresight-cti-core.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/coresight.h>
22 #include "coresight-priv.h"
23 #include "coresight-cti.h"
26 * CTI devices can be associated with a PE, or be connected to CoreSight
30 * We assume that the non-CPU CTIs are always powered as we do with sinks etc.
43 dev_get_drvdata(csdev->dev.parent)
56 * CTI device name list - for CTI not bound to cores.
60 /* write set of regs to hardware - call with spinlock claimed */
63 struct cti_config *config = &drvdata->config; in cti_write_all_hw_regs()
[all …]
Dcoresight-etm-perf.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/coresight.h>
9 #include <linux/coresight-pmu.h>
16 #include <linux/percpu-defs.h>
22 #include "coresight-config.h"
23 #include "coresight-etm-perf.h"
24 #include "coresight-priv.h"
25 #include "coresight-syscfg.h"
26 #include "coresight-trace-id.h"
65 /* preset - if sink ID is used as a configuration selector */
[all …]
Dcoresight-catu.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include "coresight-priv.h"
41 * AXI - ARPROT bits:
45 * Bit 0: 0 - Unprivileged access, 1 - Privileged access
46 * Bit 1: 0 - Secure access, 1 - Non-secure access.
47 * Bit 2: 0 - Data access, 1 - instruction access.
74 return csdev_access_relaxed_read32(&drvdata->csdev->access, offset); \
79 csdev_access_relaxed_write32(&drvdata->csdev->access, val, offset); \
86 return csdev_access_relaxed_read_pair(&drvdata->csdev->access, lo_off, hi_off); \
91 csdev_access_relaxed_write_pair(&drvdata->csdev->access, val, lo_off, hi_off); \
[all …]
Dcoresight-etm4x-core.c1 // SPDX-License-Identifier: GPL-2.0
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
34 #include <linux/clk/clk-conf.h>
42 #include "coresight-etm4x.h"
43 #include "coresight-etm-perf.h"
44 #include "coresight-etm4x-cfg.h"
45 #include "coresight-self-hosted-trace.h"
46 #include "coresight-syscfg.h"
47 #include "coresight-trace-id.h"
[all …]
/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
8 of coresight components linking the source to the sink is
9 configured and managed automatically by the coresight framework.
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
[all …]
/linux-6.12.1/arch/arm64/boot/dts/sprd/
Dsc9863a.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/sprd,sc9863a-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #address-cells = <2>;
15 #size-cells = <0>;
17 cpu-map {
48 compatible = "arm,cortex-a55";
50 enable-method = "psci";
51 cpu-idle-states = <&CORE_PD>;
56 compatible = "arm,cortex-a55";
[all …]
Dums512.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/sprd,ums512-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <2>;
18 #size-cells = <0>;
20 cpu-map {
51 compatible = "arm,cortex-a55";
[all …]
/linux-6.12.1/tools/perf/util/
Dcs-etm.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 /* PMU->type (32 bit), total # of CPUs (32 bit) */
40 * CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values
65 /* define fixed version 0 length - allow new format reader to read old files. */
66 #define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
83 /* define fixed version 0 length - allow new format reader to read old files. */
84 #define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
106 * Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
114 * table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
136 * table 6-12 Possible values for the TYPE field in an Exception instruction
[all …]
/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2p-ca15_a7.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
8 * HBI-0249A
11 /dts-v1/;
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
7 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/dma/qcom-gpi.h>
11 #include <dt-bindings/firmware/qcom,scm.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
14 #include <dt-bindings/interconnect/qcom,sm6115.h>
[all …]
Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/interconnect/qcom,msm8916.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
13 #include <dt-bindings/soc/qcom,apr.h>
[all …]
/linux-6.12.1/include/linux/
Dcoresight.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Peripheral id registers (0xFD0-0xFEC) */
26 /* Component id registers (0xFF0-0xFFC) */
78 * union coresight_dev_subtype - further characterisation of a type
99 * struct coresight_platform_data - data harvested from the firmware
118 * struct csdev_access - Abstraction of a CoreSight device access.
144 * struct coresight_desc - description of a component required from drivers
152 * in the component's sysfs sub-directory.
153 * @name: name for the coresight device, also shown under sysfs.
168 * struct coresight_connection - representation of a single connection
[all …]

123