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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
[all …]
Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MMC Controller Common Properties
10 - Ulf Hansson <ulf.hansson@linaro.org>
13 These properties are common to multiple MMC host controllers. Any host
17 It is possible to assign a fixed index mmcN to an MMC host controller
23 pattern: "^mmc(@.*)?$"
25 "#address-cells":
[all …]
Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt7986a-bananapi-bpi-r3-emmc.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
11 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
14 &{/soc/mmc@11230000} {
15 bus-width = <8>;
16 max-frequency = <200000000>;
17 cap-mmc-highspeed;
18 mmc-hs200-1_8v;
19 mmc-hs400-1_8v;
20 hs400-ds-delay = <0x14014>;
[all …]
Dmt8183-pumpkin.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
16 compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
28 stdout-path = "serial0:921600n8";
31 reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
36 scp_mem_reserved: scp-mem@50000000 {
[all …]
Dmt8188-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 /dts-v1/;
11 compatible = "mediatek,mt8188-evb", "mediatek,mt8188";
26 stdout-path = "serial0:115200n8";
34 reserved_memory: reserved-memory {
35 #address-cells = <2>;
36 #size-cells = <2>;
40 compatible = "shared-dma-pool";
42 no-map;
52 pinctrl-names = "default";
[all …]
Dmt8183-evb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
14 chassis-type = "embedded";
15 compatible = "mediatek,mt8183-evb", "mediatek,mt8183";
27 stdout-path = "serial0:921600n8";
30 reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
35 compatible = "shared-dma-pool";
37 no-map;
[all …]
Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]
Dmt8365-evk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
10 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
20 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
27 stdout-path = "serial0:921600n8";
32 compatible = "linaro,optee-tz";
37 gpio-keys {
[all …]
Dmt8195-demo.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
18 compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
25 stdout-path = "serial0:921600n8";
30 compatible = "linaro,optee-tz";
35 gpio-keys {
[all …]
Dmt8395-radxa-nio-12l.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
13 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
14 #include <dt-bindings/spmi/spmi.h>
15 #include <dt-bindings/usb/pd.h>
19 chassis-type = "embedded";
20 compatible = "radxa,nio-12l", "mediatek,mt8395", "mediatek,mt8195";
36 stdout-path = "serial0:921600n8";
[all …]
/linux-6.12.1/drivers/mmc/core/
Dhost.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/core/host.c
6 * Copyright (C) 2007-2008 Pierre Ossman
9 * MMC host class device management
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/mmc/slot-gpio.h>
29 #include "slot-gpio.h"
46 if (!host->bus_ops) in mmc_host_class_prepare()
50 if (host->bus_ops->pre_suspend) in mmc_host_class_prepare()
[all …]
/linux-6.12.1/include/linux/mmc/
Dhost.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/include/linux/mmc/host.h
12 #include <linux/fault-inject.h>
15 #include <linux/mmc/core.h>
16 #include <linux/mmc/card.h>
17 #include <linux/mmc/pm.h>
18 #include <linux/dma-direction.h>
19 #include <linux/blk-crypto-profile.h>
142 * ios->clock might be 0. For some controllers, setting 0Hz
152 * 1 for a read-only card
[all …]
/linux-6.12.1/arch/arm64/boot/dts/sprd/
Dwhale2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
66 ap-apb@70000000 {
67 compatible = "simple-bus";
[all …]
/linux-6.12.1/drivers/mmc/host/
Dsdhci-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/mmc/mmc.h>
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
123 #define INVALID_TUNING_PHASE -1
137 /* Max load for eMMC Vdd-io supply */
141 msm_host->var_ops->msm_readl_relaxed(host, offset)
144 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
[all …]
Drenesas_sdhi_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-19 Renesas Electronics Corporation
6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman
13 * Copyright 2004-2005 Phil Blundell
14 * Copyright 2007-2008 OpenedHand Ltd.
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/mmc.h>
27 #include <linux/mmc/slot-gpio.h>
30 #include <linux/pinctrl/pinctrl-state.h>
[all …]
Ddw_mmc-exynos.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
18 #include "dw_mmc-pltfm.h"
19 #include "dw_mmc-exynos.h"
21 /* Variations in Exynos specific dw-mshc controller */
52 .compatible = "samsung,exynos4210-dw-mshc",
55 .compatible = "samsung,exynos4412-dw-mshc",
58 .compatible = "samsung,exynos5250-dw-mshc",
61 .compatible = "samsung,exynos5420-dw-mshc",
[all …]
Dsdhci-of-esdhc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/dma-mapping.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/mmc.h>
26 #include "sdhci-pltfm.h"
27 #include "sdhci-esdhc.h"
71 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
72 { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk},
73 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
74 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
[all …]
Dsdhci-esdhc-imx.c1 // SPDX-License-Identifier: GPL-2.0
5 * derived from the OF-version.
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/mmc.h>
22 #include <linux/mmc/sdio.h>
23 #include <linux/mmc/slot-gpio.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
30 #include "sdhci-esdhc.h"
82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
[all …]
/linux-6.12.1/arch/riscv/boot/dts/thead/
Dth1520-lichee-module-4a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
12 compatible = "sipeed,lichee-module-4a", "thead,th1520";
21 clock-frequency = <24000000>;
25 clock-frequency = <32768>;
33 bus-width = <8>;
34 max-frequency = <198000000>;
35 mmc-hs400-1_8v;
36 non-removable;
37 no-sdio;
[all …]
Dth1520-beaglev-ahead.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
13 compatible = "beagle,beaglev-ahead", "thead,th1520";
30 stdout-path = "serial0:115200n8";
41 clock-frequency = <24000000>;
45 clock-frequency = <32768>;
53 bus-width = <8>;
54 max-frequency = <198000000>;
55 mmc-hs400-1_8v;
56 non-removable;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dqdu1000-idp.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
14 compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
15 chassis-type = "embedded";
22 stdout-path = "serial0:115200n8";
26 xo_board: xo-board-clk {
27 compatible = "fixed-clock";
28 clock-frequency = <19200000>;
29 #clock-cells = <0>;
[all …]
Dmsm8994-huawei-angler-rev-101.dts1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2021-2023, Petr Vorel <petr.vorel@gmail.com>
8 /dts-v1/;
15 chassis-type = "handset";
17 qcom,msm-id = <207 0x20000>;
18 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
19 qcom,board-id = <8026 0>;
26 stdout-path = "serial0:115200n8";
29 reserved-memory {
30 #address-cells = <2>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr8a779f0-spider-cpu.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
15 compatible = "renesas,spider-cpu", "renesas,r8a779f0";
30 stdout-path = "serial0:1843200n8";
34 compatible = "gpio-leds";
36 led-7 {
40 function-enumerator = <7>;
43 led-8 {
47 function-enumerator = <8>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/marvell/
Darmada-3720-uDPU.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include "armada-372x.dtsi"
19 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
30 led-power1 {
35 led-power2 {
40 led-network1 {
[all …]

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