Searched +full:no +full:- +full:bar +full:- +full:match +full:- +full:nbits (Results 1 – 6 of 6) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Tom Joseph <tjoseph@cadence.com>13 - $ref: /schemas/pci/pci-host-bridge.yaml#14 - $ref: cdns-pcie.yaml#17 cdns,max-outbound-regions:25 cdns,no-bar-match-nbits:27 Set into the no BAR match register to configure the number of least[all …]
1 // SPDX-License-Identifier: GPL-2.04 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>13 #include "pcie-cadence.h"33 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus()34 unsigned int busn = bus->number; in cdns_pci_map_bus()46 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()51 /* Clear AXI link-down status */ in cdns_pci_map_bus()67 if (busn == bridge->busnr + 1) in cdns_pci_map_bus()73 return rc->cfg_base + (where & 0xfff); in cdns_pci_map_bus()100 return -ETIMEDOUT; in cdns_pcie_host_training_complete()[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/phy/phy-cadence.h>9 #include <dt-bindings/phy/phy-ti.h>12 serdes_refclk: clk-0 {13 compatible = "fixed-clock";14 #clock-cells = <0>;15 clock-frequency = <0>;21 compatible = "ti,am64-wiz-10g";23 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/8 #include <dt-bindings/phy/phy-cadence.h>9 #include <dt-bindings/phy/phy-ti.h>12 serdes_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;21 compatible = "mmio-sram";23 #address-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/9 serdes_refclk: serdes-refclk {10 #clock-cells = <0>;11 compatible = "fixed-clock";17 compatible = "mmio-sram";19 #address-cells = <1>;20 #size-cells = <1>;23 atf-sram@0 {28 scm_conf: scm-conf@100000 {[all …]
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL54 * drm_printf(p, "bar=%d\n", bar);67 * struct drm_printer p = drm_info_printer(drm->dev);73 * enum drm_debug_category - The DRM debug categories85 * - drm.debug=0x1 will enable CORE messages86 * - drm.debug=0x2 will enable DRIVER messages87 * - drm.debug=0x3 will enable CORE and DRIVER messages88 * - ...89 * - drm.debug=0x1ff will enable all messages92 * run-time by echoing the debug value in its sysfs node::[all …]