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/linux-6.12.1/drivers/s390/block/
Ddasd_proc.c1 // SPDX-License-Identifier: GPL-2.0
37 device = dasd_device_from_devindex((unsigned long) v - 1); in dasd_devices_show()
40 if (device->block) in dasd_devices_show()
41 block = device->block; in dasd_devices_show()
47 seq_printf(m, "%s", dev_name(&device->cdev->dev)); in dasd_devices_show()
49 if (device->discipline != NULL) in dasd_devices_show()
50 seq_printf(m, "(%s)", device->discipline->name); in dasd_devices_show()
54 if (block->gdp) in dasd_devices_show()
56 MAJOR(disk_devt(block->gdp)), in dasd_devices_show()
57 MINOR(disk_devt(block->gdp))); in dasd_devices_show()
[all …]
/linux-6.12.1/drivers/clk/mmp/
Dclk-frac.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * mmp factor clock operation source file
9 #include <linux/clk-provider.h>
16 * It is M/N clock
19 * numerator/denominator = Fin / (Fout * factor)
27 struct mmp_clk_factor *factor = to_clk_factor(hw); in clk_factor_round_rate() local
31 for (i = 0; i < factor->ftbl_cnt; i++) { in clk_factor_round_rate()
34 rate *= factor->ftbl[i].den; in clk_factor_round_rate()
35 do_div(rate, factor->ftbl[i].num * factor->masks->factor); in clk_factor_round_rate()
40 if ((i == 0) || (i == factor->ftbl_cnt)) { in clk_factor_round_rate()
[all …]
/linux-6.12.1/drivers/iio/afe/
Diio-rescale.c1 // SPDX-License-Identifier: GPL-2.0
33 *val *= rescale->numerator; in rescale_process_scale()
34 if (rescale->denominator == 1) in rescale_process_scale()
36 *val2 = rescale->denominator; in rescale_process_scale()
44 if (!check_mul_overflow(*val, rescale->numerator, &_val) && in rescale_process_scale()
45 !check_mul_overflow(*val2, rescale->denominator, &_val2)) { in rescale_process_scale()
53 tmp = div_s64(tmp, rescale->denominator); in rescale_process_scale()
54 tmp *= rescale->numerator; in rescale_process_scale()
82 * *val = 1 and *val2 = -0.5 yields -1.5 not -0.5. in rescale_process_scale()
86 tmp = (s64)abs(*val) * abs(rescale->numerator); in rescale_process_scale()
[all …]
/linux-6.12.1/drivers/crypto/caam/
Dcaampkc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * caam - Freescale FSL CAAM support for Public Key Cryptography descriptors
17 * caam_priv_key_form - CAAM RSA private key representation
20 * 1. The first representation consists of the pair (n, d), where the
22 * n the RSA modulus
27 * p the first prime factor of the RSA modulus n
28 * q the second prime factor of the RSA modulus n
33 * p the first prime factor of the RSA modulus n
34 * q the second prime factor of the RSA modulus n
49 * caam_rsa_key - CAAM RSA key structure. Keys are allocated in DMA zone.
[all …]
/linux-6.12.1/drivers/media/platform/allegro-dvt/
Dnal-hevc.h1 /* SPDX-License-Identifier: GPL-2.0 */
14 #include <linux/v4l2-controls.h>
60 * struct nal_hevc_vps - Video parameter set
63 * Rec. ITU-T H.265 (02/2018) 7.3.2.1 Video parameter set RBSP syntax
136 * struct nal_hevc_vui_parameters - VUI parameters
138 * C struct representation of the VUI parameters as defined by Rec. ITU-T
199 * struct nal_hevc_sps - Sequence parameter set
202 * Rec. ITU-T H.265 (02/2018) 7.3.2.2 Sequence parameter set RBSP syntax
325 * nal_hevc_profile() - Get profile_idc for v4l2 hevc profile
329 * in Rec. ITU-T H.265 (02/2018) A.3.
[all …]
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt6765.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
17 #include "clk-mux.h"
18 #include "clk-pll.h"
20 #include <dt-bindings/clock/mt6765-clk.h>
83 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
84 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
85 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
[all …]
Dclk-mt6797.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>
10 #include "clk-gate.h"
11 #include "clk-mtk.h"
12 #include "clk-pll.h"
14 #include <dt-bindings/clock/mt6797-clk.h>
25 FACTOR(CLK_TOP_SYSPLL_CK, "syspll_ck", "mainpll", 1, 1),
26 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
27 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
28 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
[all …]
Dclk-mt2701.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
11 #include "clk-cpumux.h"
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-pll.h"
16 #include <dt-bindings/clock/mt2701-clk.h>
57 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
58 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
59 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
[all …]
Dclk-mt7629.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include "clk-cpumux.h"
14 #include "clk-gate.h"
15 #include "clk-mtk.h"
16 #include "clk-pll.h"
18 #include <dt-bindings/clock/mt7629-clk.h>
363 FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
364 FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
365 FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
[all …]
/linux-6.12.1/drivers/clk/actions/
Dowl-factor.c1 // SPDX-License-Identifier: GPL-2.0+
3 // OWL factor clock driver
6 // Author: David Liu <liuwei@actions-semi.com>
11 #include <linux/clk-provider.h>
14 #include "owl-factor.h"
21 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
22 if (clkt->val > maxval) in _get_table_maxval()
23 maxval = clkt->val; in _get_table_maxval()
32 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
33 if (clkt->val == val) { in _get_table_div_mul()
[all …]
/linux-6.12.1/tools/testing/selftests/syscall_user_dispatch/
Dsud_benchmark.c1 // SPDX-License-Identifier: GPL-2.0-only
37 * requires some per-architecture support (i.e. knowledge about the
39 * a small trampoline is open-coded for x86_64. Other architectures
65 int factor; variable
77 return (t2.tv_sec - t1.tv_sec) + 1.0e-9 * (t2.tv_nsec - t1.tv_nsec); in one_sysinfo_step()
84 printf("Calibrating test set to last ~%d seconds...\n", CALIBRATE_TO_SECS); in calibrate_set()
88 factor += CALIBRATE_TO_SECS; in calibrate_set()
91 printf("test iterations = %d\n", CALIBRATION_STEP * factor); in calibrate_set()
99 for (i = 0; i < factor; ++i) in perf_syscall()
100 partial += one_sysinfo_step()/(CALIBRATION_STEP*factor); in perf_syscall()
[all …]
/linux-6.12.1/drivers/media/test-drivers/vivid/
Dvivid-vid-out.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * vivid-vid-out.c - video output support functions.
12 #include <linux/v4l2-dv-timings.h>
13 #include <media/v4l2-common.h>
14 #include <media/v4l2-event.h>
15 #include <media/v4l2-dv-timings.h>
16 #include <media/v4l2-rect.h>
18 #include "vivid-core.h"
19 #include "vivid-vid-common.h"
20 #include "vivid-kthread-out.h"
[all …]
/linux-6.12.1/drivers/clk/ti/
Dfixed-factor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI Fixed Factor Clock
7 * Tero Kristo <t-kristo@ti.com>
10 #include <linux/clk-provider.h>
23 * of_ti_fixed_factor_clk_setup - Setup function for TI fixed factor clock
26 * Sets up a simple fixed factor clock based on device tree info.
36 if (of_property_read_u32(node, "ti,clock-div", &div)) { in of_ti_fixed_factor_clk_setup()
37 pr_err("%pOFn must have a clock-div property\n", node); in of_ti_fixed_factor_clk_setup()
41 if (of_property_read_u32(node, "ti,clock-mult", &mult)) { in of_ti_fixed_factor_clk_setup()
42 pr_err("%pOFn must have a clock-mult property\n", node); in of_ti_fixed_factor_clk_setup()
[all …]
/linux-6.12.1/drivers/media/platform/ti/vpe/
Dsc.c1 // SPDX-License-Identifier: GPL-2.0-only
23 struct device *dev = &sc->pdev->dev; in sc_dump_regs()
25 #define DUMPREG(r) dev_dbg(dev, "%-35s %08x\n", #r, \ in sc_dump_regs()
26 ioread32(sc->base + CFG_##r)) in sc_dump_regs()
28 dev_dbg(dev, "SC Registers @ %pa:\n", &sc->res->start); in sc_dump_regs()
84 idx = HS_LT_9_16_SCALE + sixteenths - 8; in sc_set_hs_coeffs()
99 coeff_h += SC_NUM_TAPS_MEM_ALIGN - SC_H_NUM_TAPS; in sc_set_hs_coeffs()
102 sc->load_coeff_h = true; in sc_set_hs_coeffs()
127 idx = VS_LT_9_16_SCALE + sixteenths - 8; in sc_set_vs_coeffs()
140 coeff_v += SC_NUM_TAPS_MEM_ALIGN - SC_V_NUM_TAPS; in sc_set_vs_coeffs()
[all …]
/linux-6.12.1/tools/testing/selftests/kvm/x86_64/
Dvmx_nested_tsc_scaling_test.c1 // SPDX-License-Identifier: GPL-2.0-only
18 /* L2 is scaled up (from L1's perspective) by this factor */
21 #define TSC_OFFSET_L2 ((uint64_t) -33125236320908)
42 thresh_low = expected - tolerance; in compare_tsc_freq()
69 tsc_freq = tsc_end - tsc_start; in check_tsc_freq()
137 * We set L1's scale factor to be a random number from 2 to 10. in main()
138 * Ideally we would do the same for L2's factor but that one is in main()
144 printf("L1's scale down factor is: %"PRIu64"\n", l1_scale_factor); in main()
145 printf("L2's scale up factor is: %llu\n", L2_SCALE_FACTOR); in main()
151 l0_tsc_freq = tsc_end - tsc_start; in main()
[all …]
/linux-6.12.1/drivers/clk/sunxi/
Dclk-factors.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Adjustable factor-based clock implementation
8 #include <linux/clk-provider.h>
16 #include "clk-factors.h"
19 * DOC: basic adjustable factor-based clock
22 * prepare - clk_prepare only ensures that parents are prepared
23 * enable - clk_enable only ensures that parents are enabled
24 * rate - rate is adjustable.
25 * clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
26 * parent - fixed parent. No clk_set_parent support
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/hwmon/
Dti,tmp421.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guenter Roeck <linux@roeck-us.net>
19 - ti,tmp421
20 - ti,tmp422
21 - ti,tmp423
22 - ti,tmp441
23 - ti,tmp442
27 '#address-cells':
[all …]
Dti,tmp464.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guenter Roeck <linux@roeck-us.net>
20 - ti,tmp464
21 - ti,tmp468
26 '#address-cells':
29 '#size-cells':
33 - compatible
34 - reg
[all …]
Dti,tmp401.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guenter Roeck <linux@roeck-us.net>
24 - ti,tmp401
25 - ti,tmp411
26 - ti,tmp431
27 - ti,tmp432
28 - ti,tmp435
33 ti,extended-range-enable:
[all …]
/linux-6.12.1/drivers/gpu/drm/sprd/
Dmegacores_pll.c1 // SPDX-License-Identifier: GPL-2.0
22 #define AVERAGE(a, b) (min(a, b) + abs((b) - (a)) / 2)
34 const unsigned long long factor = 100; in dphy_calc_pll_param() local
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
42 if (pll->potential_fvco >= VCO_BAND_LOW && in dphy_calc_pll_param()
43 pll->potential_fvco <= VCO_BAND_HIGH) { in dphy_calc_pll_param()
44 pll->fvco = pll->potential_fvco; in dphy_calc_pll_param()
45 pll->out_sel = BIT(i); in dphy_calc_pll_param()
48 pll->potential_fvco <<= 1; in dphy_calc_pll_param()
[all …]
/linux-6.12.1/drivers/thermal/
Damlogic_thermal.c1 // SPDX-License-Identifier: GPL-2.0+
10 * U = ---------, Uptat = ---------
11 * 2^16 1 + n * U
13 * Temperature = A * ( Uptat + u_efuse / 2^16 )- B
15 * A B m n : calibration parameters
71 * @n: calibration parameters
79 int n; member
113 pdata->data->calibration_parameters; in amlogic_thermal_code_to_millicelsius()
115 s64 factor, Uptat, uefuse; in amlogic_thermal_code_to_millicelsius() local
117 uefuse = pdata->trim_info & TSENSOR_TRIM_SIGN_MASK ? in amlogic_thermal_code_to_millicelsius()
[all …]
Dthermal_mmio.c1 // SPDX-License-Identifier: GPL-2.0
15 int factor; member
28 t = sensor->read_mmio(sensor->mmio_base) & sensor->mask; in thermal_mmio_get_temperature()
29 t *= sensor->factor; in thermal_mmio_get_temperature()
49 sensor = devm_kzalloc(&pdev->dev, sizeof(*sensor), GFP_KERNEL); in thermal_mmio_probe()
51 return -ENOMEM; in thermal_mmio_probe()
53 sensor->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); in thermal_mmio_probe()
54 if (IS_ERR(sensor->mmio_base)) in thermal_mmio_probe()
55 return PTR_ERR(sensor->mmio_base); in thermal_mmio_probe()
57 sensor_init_func = device_get_match_data(&pdev->dev); in thermal_mmio_probe()
[all …]
/linux-6.12.1/drivers/clocksource/
Dtimer-cadence-ttc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2013 Xilinx
23 * This driver configures the 2 16/32-bit count-up timers as follows:
30 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
34 * obtained from device tree. The pre-scaler of 32 is used.
55 * Setup the timers to use pre-scaling, using a fixed value for now that will
60 #define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
67 * struct ttc_timer - This definition defines local timer structure
105 * ttc_set_interval - Set the timer interval value
115 /* Disable the counter, set the counter value and re-enable counter */ in ttc_set_interval()
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
10 #include <linux/clk-provider.h>
11 #include <linux/interconnect-clk.h>
12 #include <linux/reset-controller.h>
16 #include "clk-rcg.h"
17 #include "clk-regmap.h"
33 if (!f->freq) in qcom_find_freq()
36 for (; f->freq; f++) in qcom_find_freq()
37 if (rate <= f->freq) in qcom_find_freq()
[all …]
/linux-6.12.1/drivers/clk/
Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
[all …]

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