Home
last modified time | relevance | path

Searched full:mux_reg (Results 1 – 25 of 66) sorted by relevance

123

/linux-6.12.1/arch/arm/mach-omap1/
Dmux.h27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \ macro
28 .mux_reg = FUNC_MUX_CTRL_##reg, \
42 .mux_reg = OMAP7XX_IO_CONF_##reg, \
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ macro
65 .mux_reg = OMAP7XX_IO_CONF_##reg, \
75 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ argument
81 MUX_REG(mux_reg, mode_offset, mode) \
94 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode, \ argument
99 MUX_REG_7XX(mux_reg, mode_offset, mode) \
100 PULL_REG_7XX(mux_reg, pull_bit, pull_status) \
[all …]
/linux-6.12.1/drivers/pinctrl/tegra/
Dpinctrl-tegra.c260 if (WARN_ON(g->mux_reg < 0)) in tegra_pinctrl_set_mux()
270 val = pmx_readl(pmx, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
273 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); in tegra_pinctrl_set_mux()
316 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_request_enable()
319 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
321 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_request_enable()
342 if (group->mux_reg < 0 || group->sfsel_bit < 0) in tegra_pinctrl_gpio_disable_free()
345 value = pmx_readl(pmx, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
347 pmx_writel(pmx, value, group->mux_bank, group->mux_reg); in tegra_pinctrl_gpio_disable_free()
380 *reg = g->mux_reg; in tegra_pinconf_reg()
[all …]
Dpinctrl-tegra.h92 * @mux_reg: Mux register offset.
144 s32 mux_reg; member
/linux-6.12.1/drivers/clk/samsung/
Dclk-cpu.c143 static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos, in wait_until_mux_stable() argument
149 if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) in wait_until_mux_stable()
153 if (((readl(mux_reg) >> mux_pos) & mask) == mux_value) in wait_until_mux_stable()
203 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
256 mux_reg = readl(base + regs->mux_sel); in exynos_cpuclk_pre_rate_change()
257 writel(mux_reg | (1 << 16), base + regs->mux_sel); in exynos_cpuclk_pre_rate_change()
282 unsigned long mux_reg; in exynos_cpuclk_post_rate_change() local
297 mux_reg = readl(base + regs->mux_sel); in exynos_cpuclk_post_rate_change()
298 writel(mux_reg & ~(1 << 16), base + regs->mux_sel); in exynos_cpuclk_post_rate_change()
330 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
[all …]
/linux-6.12.1/drivers/clk/qcom/
Dlpass-gfm-sm8250.c29 unsigned int mux_reg; member
70 .mux_reg = 0x20000,
90 .mux_reg = 0x20000,
110 .mux_reg = 0x220d8,
130 .mux_reg = 0x220d8,
150 .mux_reg = 0x240d8,
170 .mux_reg = 0x240d8,
275 gfm->gfm_mux = gfm->gfm_mux + data->gfm_clks[i]->mux_reg; in lpass_gfm_clk_driver_probe()
/linux-6.12.1/drivers/pinctrl/freescale/
Dpinctrl-imx.c176 if (pin_reg->mux_reg == -1) { in imx_pmx_set_one_pin_mmio()
185 reg = readl(ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
188 writel(reg, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
190 pin_reg->mux_reg, reg); in imx_pmx_set_one_pin_mmio()
192 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
194 pin_reg->mux_reg, pin_mmio->mux_mode); in imx_pmx_set_one_pin_mmio()
450 * <mux_reg conf_reg input_reg mux_mode input_val>
469 u32 mux_reg, conf_reg; in imx_pinctrl_parse_pin_mmio() local
472 mux_reg = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
474 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) in imx_pinctrl_parse_pin_mmio()
[all …]
Dpinctrl-imx8ulp.c229 if (pin_reg->mux_reg == -1) in imx8ulp_pmx_gpio_set_direction()
232 reg = readl(ipctl->base + pin_reg->mux_reg); in imx8ulp_pmx_gpio_set_direction()
237 writel(reg, ipctl->base + pin_reg->mux_reg); in imx8ulp_pmx_gpio_set_direction()
Dpinctrl-imx7ulp.c270 if (pin_reg->mux_reg == -1) in imx7ulp_pmx_gpio_set_direction()
273 reg = readl(ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
278 writel(reg, ipctl->base + pin_reg->mux_reg); in imx7ulp_pmx_gpio_set_direction()
Dpinctrl-imx.h61 * @mux_reg: mux register offset
65 s16 mux_reg; member
Dpinctrl-vf610.c302 if (pin_reg->mux_reg == -1) in vf610_pmx_gpio_set_direction()
306 reg = readl(ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
311 writel(reg, ipctl->base + pin_reg->mux_reg); in vf610_pmx_gpio_set_direction()
Dpinctrl-imx-scmi.c65 int mux_reg, conf_reg, input_reg, mux_val, conf_val, input_val; in pinctrl_scmi_imx_dt_node_to_map() local
107 mux_reg = be32_to_cpu(*list++); in pinctrl_scmi_imx_dt_node_to_map()
116 pin_id = mux_reg / 4; in pinctrl_scmi_imx_dt_node_to_map()
/linux-6.12.1/arch/arm/mach-davinci/
Dmux.c68 reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
80 __raw_writel(reg, pinmux_base + cfg->mux_reg); in davinci_cfg_reg()
94 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); in davinci_cfg_reg()
Dmux.h17 const unsigned char mux_reg; member
668 .mux_reg = PINMUX(muxreg), \
679 .mux_reg = INTMUX, \
690 .mux_reg = EVTMUX, \
/linux-6.12.1/sound/soc/tegra/
Dtegra210_ahub.h39 #define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id)) macro
60 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
69 SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dnxp,imx95-scmi-pinctrl.yaml29 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
38 "mux_reg" indicates the offset of mux register.
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dfsl,imxrt1050.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
45 "mux_reg" indicates the offset of mux register.
Dfsl,imxrt1170.yaml36 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
45 "mux_reg" indicates the offset of mux register.
Dfsl,imx9-pinctrl.yaml40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
Dfsl,imx8m-pinctrl.yaml39 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
Dfsl,imx6ul-pinctrl.yaml40 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
49 "mux_reg" indicates the offset of mux register.
Dfsl,imx7d-pinctrl.yaml44 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
53 "mux_reg" indicates the offset of mux register.
Dfsl,imx6sx-pinctrl.txt9 setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mtk.h96 uint32_t mux_reg; member
116 .mux_reg = _reg, \
152 .mux_reg = _reg, \
/linux-6.12.1/drivers/clk/microchip/
Dclk-core.c763 void __iomem *mux_reg; member
824 v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_get_parent()
848 v = readl(sclk->mux_reg); in sclk_set_parent()
854 writel(v, sclk->mux_reg); in sclk_set_parent()
857 writel(OSC_SWEN, PIC32_SET(sclk->mux_reg)); in sclk_set_parent()
875 cosc = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK; in sclk_set_parent()
939 sclk->mux_reg = data->mux_reg + core->iobase; in pic32_sys_clk_register()
/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx6ull-pinfunc-snvs.h11 * <mux_reg conf_reg input_reg mux_mode input_val>

123