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/linux-6.12.1/Documentation/devicetree/bindings/mux/
Dmux-consumer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
[all …]
Dadi,adgs1408.txt1 Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux
4 - compatible : Should be one of
7 * Standard mux-controller bindings as described in mux-controller.yaml
10 - gpio-controller : if present, #gpio-cells is required.
11 - #gpio-cells : should be <2>
12 - First cell is the GPO line number, i.e. 0 to 3
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, the state that the mux controller will have
22 States 0 through 7 correspond to signals S1 through S8 in the datasheet.
23 For ADGS1409 only states 0 to 3 are available.
[all …]
Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
19 A mux controller provides a number of states to its consumers, and the state
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
[all …]
Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, array of states that the mux controllers will have
[all …]
Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
[all …]
/linux-6.12.1/drivers/i2c/muxes/
Di2c-mux-pinctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/i2c-mux.h>
19 struct pinctrl_state *states[]; member
24 struct i2c_mux_pinctrl *mux = i2c_mux_priv(muxc); in i2c_mux_pinctrl_select() local
26 return pinctrl_select_state(mux->pinctrl, mux->states[chan]); in i2c_mux_pinctrl_select()
31 return i2c_mux_pinctrl_select(muxc, muxc->num_adapters); in i2c_mux_pinctrl_deselect()
41 list_for_each_entry(setting, &state->settings, node) { in i2c_mux_pinctrl_root_adapter()
42 pin_root = i2c_root_adapter(setting->pctldev->dev); in i2c_mux_pinctrl_root_adapter()
56 struct device_node *np = dev->of_node; in i2c_mux_pinctrl_parent_adapter()
60 parent_np = of_parse_phandle(np, "i2c-parent", 0); in i2c_mux_pinctrl_parent_adapter()
[all …]
/linux-6.12.1/include/linux/mux/
Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mux/driver.h - definitions for the multiplexer driver interface
13 #include <dt-bindings/mux/mux.h>
22 * struct mux_control_ops - Mux controller operations for a mux chip.
23 * @set: Set the state of the given mux controller.
26 int (*set)(struct mux_control *mux, int state);
30 * struct mux_control - Represents a mux controller.
31 * @lock: Protects the mux controller state.
32 * @chip: The mux chip that is handling this mux controller.
33 * @cached_state: The current mux controller state, or -1 if none.
[all …]
/linux-6.12.1/drivers/mux/
Dadgs1408.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ADGS1408/ADGS1409 SPI MUX driver
11 #include <linux/mux/driver.h>
36 static int adgs1408_set(struct mux_control *mux, int state) in adgs1408_set() argument
38 struct spi_device *spi = to_spi_device(mux->chip->dev.parent); in adgs1408_set()
55 struct device *dev = &spi->dev; in adgs1408_probe()
58 struct mux_control *mux; in adgs1408_probe() local
64 chip_id = spi_get_device_id(spi)->driver_data; in adgs1408_probe()
70 mux_chip->ops = &adgs1408_ops; in adgs1408_probe()
76 ret = device_property_read_u32(dev, "idle-state", (u32 *)&idle_state); in adgs1408_probe()
[all …]
Dgpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO-controlled multiplexer driver
15 #include <linux/mux/driver.h>
23 static int mux_gpio_set(struct mux_control *mux, int state) in mux_gpio_set() argument
25 struct mux_gpio *mux_gpio = mux_chip_priv(mux->chip); in mux_gpio_set()
31 gpiod_set_array_value_cansleep(mux_gpio->gpios->ndescs, in mux_gpio_set()
32 mux_gpio->gpios->desc, in mux_gpio_set()
33 mux_gpio->gpios->info, values); in mux_gpio_set()
43 { .compatible = "gpio-mux", },
50 struct device *dev = &pdev->dev; in mux_gpio_probe()
[all …]
Dcore.c1 // SPDX-License-Identifier: GPL-2.0
10 #define pr_fmt(fmt) "mux-core: " fmt
19 #include <linux/mux/consumer.h>
20 #include <linux/mux/driver.h>
25 * The idle-as-is "state" is not an actual state that may be selected, it
32 * struct mux_state - Represents a mux controller state specific to a given
34 * @mux: Pointer to a mux controller.
35 * @state: State of the mux to be selected.
41 struct mux_control *mux; member
46 .name = "mux",
[all …]
Dmmio.c1 // SPDX-License-Identifier: GPL-2.0
3 * MMIO register bitfield-controlled multiplexer driver
12 #include <linux/mux/driver.h>
18 static int mux_mmio_set(struct mux_control *mux, int state) in mux_mmio_set() argument
20 struct regmap_field **fields = mux_chip_priv(mux->chip); in mux_mmio_set()
22 return regmap_field_write(fields[mux_control_get_index(mux)], state); in mux_mmio_set()
30 { .compatible = "mmio-mux", },
31 { .compatible = "reg-mux", },
38 struct device *dev = &pdev->dev; in mux_mmio_probe()
39 struct device_node *np = dev->of_node; in mux_mmio_probe()
[all …]
DKconfig1 # SPDX-License-Identifier: GPL-2.0
22 be called mux-adg792a.
32 be called mux-adgs1408.
35 tristate "GPIO-controlled Multiplexer"
38 GPIO-controlled Multiplexer controller.
42 states. The GPIO pins can be connected (by the hardware) to several
46 be called mux-gpio.
49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
56 bitfields, there will be 2^N possible multiplexer states.
[all …]
Dadg792a.c1 // SPDX-License-Identifier: GPL-2.0
3 * Multiplexer driver for Analog Devices ADG792A/G Triple 4:1 mux
13 #include <linux/mux/driver.h>
18 #define ADG792A_DISABLE(mux) (0x50 | (mux)) argument
20 #define ADG792A_MUX(mux, state) (0xc0 | (((mux) + 1) << 2) | (state)) argument
34 static int adg792a_set(struct mux_control *mux, int state) in adg792a_set() argument
36 struct i2c_client *i2c = to_i2c_client(mux->chip->dev.parent); in adg792a_set()
39 if (mux->chip->controllers == 1) { in adg792a_set()
40 /* parallel mux controller operation */ in adg792a_set()
46 unsigned int controller = mux_control_get_index(mux); in adg792a_set()
[all …]
/linux-6.12.1/include/net/
Dbond_3ad.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
31 /* rx machine states(43.4.11 in the 802.3ad standard) */
42 /* periodic machine states(43.4.12 in the 802.3ad standard) */
51 /* mux machine states(43.4.13 in the 802.3ad standard) */
54 AD_MUX_DETACHED, /* mux machine */
55 AD_MUX_WAITING, /* mux machine */
56 AD_MUX_ATTACHED, /* mux machine */
57 AD_MUX_COLLECTING, /* mux machine */
58 AD_MUX_DISTRIBUTING, /* mux machine */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dti,tcan104x-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Aswath Govindraju <a-govindraju@ti.com>
14 pattern: "^can-phy"
18 - nxp,tjr1443
19 - ti,tcan1042
20 - ti,tcan1043
22 '#phy-cells':
[all …]
/linux-6.12.1/include/dt-bindings/pinctrl/
Domap.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2009-2010 Texas Instruments
12 /* 34xx mux mode options for each pin. See TRM for options */
22 /* 24xx/34xx mux bit defines */
27 /* omap3/4/5 specific mux bit defines */
37 /* Active pin states */
45 /* Off mode states */
57 #define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
68 #define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) argument
74 #define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
/linux-6.12.1/Documentation/devicetree/bindings/iio/multiplexer/
Dio-channel-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
16 For each non-empty string in the channels property, an io-channel will be
17 created. The number of this io-channel is the same as the index into the list
18 of strings in the channels property, and also matches the mux controller
19 state. The mux controller state is described in
20 Documentation/devicetree/bindings/mux/mux-controller.yaml
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dnxp,imx95-display-master-csr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
15 - const: nxp,imx95-display-master-csr
16 - const: syscon
21 power-domains:
27 '#clock-cells':
32 include/dt-bindings/clock/nxp,imx95-clock.h
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/nuvoton/
Dnuvoton,npcm-gcr.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-gcr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
11 - Tomer Maimon <tmaimon77@gmail.com>
21 - enum:
22 - nuvoton,wpcm450-gcr
23 - nuvoton,npcm750-gcr
24 - nuvoton,npcm845-gcr
[all …]
/linux-6.12.1/drivers/pinctrl/
Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
78 * struct pinctrl - per-device pin control state holder
81 * @states: a list of states for this device
90 struct list_head states; member
97 * struct pinctrl_state - a pinctrl state for a device
98 * @node: list node for struct pinctrl's @states field
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
[all …]
/linux-6.12.1/drivers/net/wwan/iosm/
Diosm_ipc_mux.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2020-21 Intel Corporation.
19 /* Size of the buffer for the IP MUX Lite data buffer. */
22 /* TD counts for IP MUX Lite */
26 /* open session request (AP->CP) */
29 /* response to open session request (CP->AP) */
32 /* close session request (AP->CP) */
35 /* response to close session request (CP->AP) */
58 /* MUX for route link devices */
61 /* Initiated actions to change the state of the MUX object. */
[all …]
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Drzg3s-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 * On-board switches' states:
20 * SW_CONFIG[x] switches' states:
22 * SW_OFF - SD0 is connected to eMMC
23 * SW_ON - SD0 is connected to uSD0 card
25 * SW_OFF - SD2 is connected to SoC
26 * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
[all …]
/linux-6.12.1/Documentation/driver-api/
Ddpll.rst1 .. SPDX-License-Identifier: GPL-2.0
10 PLL - Phase Locked Loop is an electronic circuit which syntonizes clock
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
76 differences for each mode in terms of available pin states, as well as
77 for the states the user can request for a dpll device.
80 one of following pin states:
82 - ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device
83 - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll
87 receive one of following pin states:
89 - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid
[all …]
/linux-6.12.1/drivers/phy/
Dphy-can-transceiver.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-can-transceiver.c - phy driver for CAN transceivers
5 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
14 #include <linux/mux/consumer.h>
35 if (can_transceiver_phy->mux_state) { in can_transceiver_phy_power_on()
36 ret = mux_state_select(can_transceiver_phy->mux_state); in can_transceiver_phy_power_on()
38 dev_err(&phy->dev, "Failed to select CAN mux: %d\n", ret); in can_transceiver_phy_power_on()
42 if (can_transceiver_phy->standby_gpio) in can_transceiver_phy_power_on()
43 gpiod_set_value_cansleep(can_transceiver_phy->standby_gpio, 0); in can_transceiver_phy_power_on()
44 if (can_transceiver_phy->enable_gpio) in can_transceiver_phy_power_on()
[all …]

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