| /linux-6.12.1/sound/soc/codecs/ |
| D | tlv320aic32x4-clk.c | 26 * struct clk_aic32x4_pll_muldiv - Multiplier/divider settings
28 * @r: first multiplier
29 * @j: integer part of second multiplier
30 * @d: decimal part of second multiplier
157 u64 multiplier; in clk_aic32x4_pll_calc_muldiv() local
165 * of the multiplier. This is because we can't do floating point in clk_aic32x4_pll_calc_muldiv()
168 multiplier = (u64) rate * settings->p * 10000; in clk_aic32x4_pll_calc_muldiv()
169 do_div(multiplier, parent_rate); in clk_aic32x4_pll_calc_muldiv()
175 settings->r = ((u32) multiplier / 640000) + 1; in clk_aic32x4_pll_calc_muldiv()
178 do_div(multiplier, settings->r); in clk_aic32x4_pll_calc_muldiv()
[all …]
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| /linux-6.12.1/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi_audio.c | 114 uint32_t n, cts, multiplier; in msm_hdmi_audio_update() local
123 multiplier = 4; in msm_hdmi_audio_update()
124 n >>= 2; /* divide N by 4 and use multiplier */ in msm_hdmi_audio_update()
127 multiplier = 2; in msm_hdmi_audio_update()
128 n >>= 1; /* divide N by 2 and use multiplier */ in msm_hdmi_audio_update()
130 multiplier = 1; in msm_hdmi_audio_update()
133 DBG("n=%u, cts=%u, multiplier=%u", n, cts, multiplier); in msm_hdmi_audio_update()
137 acr_pkt_ctrl |= HDMI_ACR_PKT_CTRL_N_MULTIPLIER(multiplier); in msm_hdmi_audio_update()
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | keystone-pll.txt | 1 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
27 reg-names = "control", "multiplier", "post-divider";
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| /linux-6.12.1/drivers/clk/ |
| D | clk-vt8500.c | 351 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits() argument
358 *multiplier = 0; in vt8500_find_pll_bits()
368 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
369 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
390 unsigned long parent_rate, u32 *multiplier, u32 *divisor1, in wm8650_find_pll_bits() argument
409 *multiplier = O1 / parent_rate; in wm8650_find_pll_bits()
417 if ((*multiplier < 3) || (*multiplier > 1023)) in wm8650_find_pll_bits()
453 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2) in wm8750_find_pll_bits() argument
472 *multiplier = mul; in wm8750_find_pll_bits()
480 *multiplier = mul; in wm8750_find_pll_bits()
[all …]
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| /linux-6.12.1/tools/power/cpupower/debug/i386/ |
| D | centrino-decode.c | 65 unsigned int multiplier; in decode() local
68 multiplier = ((msr >> 8) & 0xFF); in decode()
72 printf("0x%x means multiplier %d @ %d mV\n", msr, multiplier, mv); in decode()
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| /linux-6.12.1/drivers/clk/ti/ |
| D | dpll44xx.c | 34 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
83 * multiplier and divider values calculated. If low-power mode can be
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
166 * target rate without using the 4X multiplier. in omap4_dpll_regm4xen_round_rate()
174 * this time see if using the 4X multiplier can help. Enabling the in omap4_dpll_regm4xen_round_rate()
175 * 4X multiplier is equivalent to dividing the target rate by 4. in omap4_dpll_regm4xen_round_rate()
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| D | clkt_dpll.c | 25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
121 * _dpll_test_mult - test a DPLL multiplier value
122 * @m: pointer to the DPLL m (multiplier) value under test
128 * This code tests a DPLL multiplier value, ensuring that the
130 * the multiplier value itself is valid for the DPLL. Initially, the
323 /* Compute the scaled DPLL multiplier, based on the divider */ in omap2_dpll_round_rate()
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| /linux-6.12.1/drivers/clk/keystone/ |
| D | pll.c | 27 * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
35 * @pllm: PLL register map address for multiplier bits
38 * @pllm_lower_mask: multiplier lower mask
39 * @pllm_upper_mask: multiplier upper mask
40 * @pllm_upper_shift: multiplier upper shift
84 * get bits 0-5 of multiplier from pllctrl PLLM register in clk_pllclk_recalc()
155 * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
202 i = of_property_match_string(node, "reg-names", "multiplier"); in _of_pll_clk_init()
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| /linux-6.12.1/drivers/cpufreq/ |
| D | powernow-k6.c | 33 MODULE_PARM_DESC(max_multiplier, "Maximum multiplier (allowed values: 20 30 35 40 45 50 55 60)");
78 * powernow_k6_get_cpu_multiplier - returns the current FSB multiplier
80 * Returns the current setting of the frequency multiplier. Core clock
134 * powernow_k6_target - set the PowerNow! multiplier
135 * @best_i: clock_ratio[best_i] is the target multiplier
137 * Tries to change the PowerNow! multiplier
183 pr_warn("unknown frequency %u, cannot determine current multiplier\n", in powernow_k6_cpu_init()
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| D | e_powersaver.c | 125 /* Set new multiplier and voltage */ in eps_set_state()
142 /* Print voltage and multiplier */ in eps_set_state()
147 pr_info("Current multiplier = %d\n", current_multiplier); in eps_set_state()
240 /* Print voltage and multiplier */ in eps_cpu_init()
245 pr_info("Current multiplier = %d\n", current_multiplier); in eps_cpu_init()
251 pr_info("Highest multiplier = %d\n", max_multiplier); in eps_cpu_init()
255 pr_info("Lowest multiplier = %d\n", min_multiplier); in eps_cpu_init()
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| /linux-6.12.1/include/uapi/linux/netfilter/ |
| D | xt_hashlimit.h | 35 __u32 burst; /* Period multiplier for upper limit. */
59 __u32 burst; /* Period multiplier for upper limit. */
72 __u64 burst; /* Period multiplier for upper limit. */
86 __u64 burst; /* Period multiplier for upper limit. */
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| /linux-6.12.1/drivers/video/fbdev/aty/ |
| D | mach64_ct.c | 121 u32 multiplier, divider, ras_multiplier, ras_divider, tmp; in aty_dsp_gt() local
125 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
143 multiplier = multiplier * par->lcd_width; in aty_dsp_gt()
150 /* If we don't do this, 32 bits for multiplier & divider won't be in aty_dsp_gt()
152 while (((multiplier | divider) & 1) == 0) { in aty_dsp_gt()
153 multiplier = multiplier >> 1; in aty_dsp_gt()
158 tmp = ((multiplier * pll->fifo_size) << vshift) / divider; in aty_dsp_gt()
171 dsp_off = ((multiplier * (pll->fifo_size - 1)) << vshift) / divider - in aty_dsp_gt()
175 dsp_on = ((multiplier * 20 << vshift) + divider) / divider; in aty_dsp_gt()
178 dsp_on = ((multiplier << vshift) + divider) / divider; in aty_dsp_gt()
[all …]
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| /linux-6.12.1/samples/hid/ |
| D | hid_surface_dial.bpf.c | 78 /* whenever resolution multiplier is not 3600, we have the fixed report descriptor */ in set_haptic()
81 // haptic_data[1] = 72; /* resolution multiplier */ in set_haptic()
82 // haptic_data[2] = 0; /* resolution multiplier */ in set_haptic()
120 /* Change Resolution Multiplier */ in BPF_PROG()
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| /linux-6.12.1/drivers/net/ethernet/pensando/ionic/ |
| D | ionic_phc.c | 335 /* Final adjusted multiplier */ in ionic_phc_adjfine()
549 "Invalid device PHC mask multiplier %u, disabling HW timestamp support\n", in ionic_lif_alloc_phc()
562 /* max ticks is limited by the multiplier, or by the update period. */ in ionic_lif_alloc_phc()
565 * adjusted multiplier (twice the initial multiplier) in ionic_lif_alloc_phc()
593 * adjust the initial multiplier, being careful to avoid overflow: in ionic_lif_alloc_phc()
597 * we want to increase the initial multiplier as much as possible, to in ionic_lif_alloc_phc()
600 * only adjust the multiplier if we can double it or more. in ionic_lif_alloc_phc()
605 /* initial multiplier will be 2^n of hardware cc.mult */ in ionic_lif_alloc_phc()
615 /* frequency adjustments are relative to the initial multiplier */ in ionic_lif_alloc_phc()
629 /* We have allowed to adjust the multiplier up to +/- 1 part per 1. in ionic_lif_alloc_phc()
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| /linux-6.12.1/Documentation/devicetree/bindings/dma/ |
| D | img-mdc-dma.txt | 13 - img,max-burst-multiplier: Must be the maximum supported burst size multiplier.
46 img,max-burst-multiplier = <16>;
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| /linux-6.12.1/drivers/ata/ |
| D | ahci_da850.c | 49 * We need to determine the value of the multiplier (MPY) bits. in ahci_da850_calculate_mpy()
50 * In order to include the 12.5 multiplier we need to first divide in ahci_da850_calculate_mpy()
60 * What we have now is (multiplier * 10). in ahci_da850_calculate_mpy()
102 * enable Port Multiplier support, but the drive is connected directly in ahci_da850_softreset()
197 dev_err(dev, "invalid REFCLK multiplier value: 0x%x", mpy); in ahci_da850_probe()
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| /linux-6.12.1/drivers/usb/gadget/function/ |
| D | u_ether.h | 29 MODULE_PARM_DESC(qmult, "queue length multiplier at high/super speed");\
220 * gether_set_qmult - initialize an ethernet-over-usb link with a multiplier
222 * @qmult: queue multiplier
224 * This sets the queue length multiplier of this ethernet-over-usb link.
230 * gether_get_qmult - get an ethernet-over-usb link multiplier
233 * This gets the queue length multiplier of this ethernet-over-usb link.
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| /linux-6.12.1/arch/mips/ath25/ |
| D | ar5312.c | 289 unsigned predivide_select, predivisor, multiplier; in ar5312_cpu_frequency() local
315 * cpu_freq = input_clock * MULT (where MULT is PLL multiplier) in ar5312_cpu_frequency()
321 * So, for example, with a PLL multiplier of 5, we have in ar5312_cpu_frequency()
333 multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift; in ar5312_cpu_frequency()
336 multiplier <<= 1; in ar5312_cpu_frequency()
338 return (40000000 / predivisor) * multiplier; in ar5312_cpu_frequency()
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| /linux-6.12.1/arch/mips/sibyte/swarm/ |
| D | rtc_m41t81.c | 35 #define M41T81REG_WD_BMB0 0x04 /* watchdog multiplier bit 0 */
36 #define M41T81REG_WD_BMB1 0x08 /* watchdog multiplier bit 1 */
37 #define M41T81REG_WD_BMB2 0x10 /* watchdog multiplier bit 2 */
38 #define M41T81REG_WD_BMB3 0x20 /* watchdog multiplier bit 3 */
39 #define M41T81REG_WD_BMB4 0x40 /* watchdog multiplier bit 4 */
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| /linux-6.12.1/drivers/clk/at91/ |
| D | clk-pll.c | 143 * Calculate minimum divider based on the minimum multiplier, the in clk_pll_get_best_div_mul()
171 * divider/multiplier pair (the one that generates the closest in clk_pll_get_best_div_mul()
180 * Calculate the multiplier associated with the current in clk_pll_get_best_div_mul()
192 * now and elect a new best multiplier/divider pair if the in clk_pll_get_best_div_mul()
204 * Stop searching now and use this multiplier/divider pair. in clk_pll_get_best_div_mul()
210 /* We haven't found any multiplier/divider pair => return -ERANGE */ in clk_pll_get_best_div_mul()
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| /linux-6.12.1/drivers/net/ethernet/intel/ixgbe/ |
| D | ixgbe_dcb.c | 25 int min_credit, multiplier; in ixgbe_ieee_credits() local
36 multiplier = (min_credit / min_percent) + 1; in ixgbe_ieee_credits()
40 int val = min(bw[i] * multiplier, MAX_CREDIT_REFILL); in ixgbe_ieee_credits()
98 * a multiplier. It is required that the refill credits must be in ixgbe_dcb_calculate_tc_credits()
100 * multiplier that will allow all bandwidth percentages to be in ixgbe_dcb_calculate_tc_credits()
119 /* Calculate credit refill ratio using multiplier */ in ixgbe_dcb_calculate_tc_credits()
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| /linux-6.12.1/drivers/clk/pxa/ |
| D | clk-pxa2xx.h | 10 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
11 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
12 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
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| /linux-6.12.1/lib/raid6/ |
| D | recov_neon.c | 27 const u8 *pbmul; /* P multiplier table for B data */ in raid6_2data_recov_neon()
28 const u8 *qmul; /* Q multiplier table (for both) */ in raid6_2data_recov_neon()
67 const u8 *qmul; /* Q multiplier table */ in raid6_datap_recov_neon()
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| /linux-6.12.1/drivers/clk/ingenic/ |
| D | cgu.h | 20 * @rate_multiplier: the multiplier needed by pll rate calculation
21 * @m_shift: the number of bits to shift the multiplier value by (ie. the
22 * index of the lowest bit of the multiplier value in the PLL's
24 * @m_bits: the size of the multiplier field in bits
25 * @m_offset: the multiplier value which encodes to 0 in the PLL's control
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| /linux-6.12.1/arch/microblaze/include/asm/ |
| D | hash.h | 7 * both multiplier and barrel shifter, but omitting them is technically
15 * That software is really not designed for a single multiplier this large,
57 * optimal, but at 37 steps, it's decent for a 31-bit multiplier. in __hash_32()
|