| /linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/ |
| D | stmmac_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2011 STMicroelectronics Ltd
26 * dwmac1000_validate_mcast_bins - validates the number of Multicast filter bins
28 * @mcast_bins: Multicast filtering bins
30 * this function validates the number of Multicast filtering bins specified
32 * 64 bins, 128 bins, or 256 bins. "bins" refer to the division of CRC
33 * number space. 64 bins correspond to 6 bits of the CRC, 128 corresponds
35 * invalid and will cause the filtering algorithm to use Multicast
57 * dwmac1000_validate_ucast_entries - validate the Unicast address entries
63 * supports 1..32, 64, or 128 Unicast filter entries for it's Unicast filter
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| D | dwmac-generic.c | 4 * Copyright (C) 2007-2011 STMicroelectronics Ltd
29 if (pdev->dev.of_node) { in dwmac_generic_probe()
32 dev_err(&pdev->dev, "dt configuration failed\n"); in dwmac_generic_probe()
36 plat_dat = dev_get_platdata(&pdev->dev); in dwmac_generic_probe()
38 dev_err(&pdev->dev, "no platform data provided\n"); in dwmac_generic_probe()
39 return -EINVAL; in dwmac_generic_probe()
42 /* Set default value for multicast hash bins */ in dwmac_generic_probe()
43 plat_dat->multicast_filter_bins = HASH_TABLE_SIZE; in dwmac_generic_probe()
45 /* Set default value for unicast filter entries */ in dwmac_generic_probe()
46 plat_dat->unicast_filter_entries = 1; in dwmac_generic_probe()
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| D | stmmac_pci.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2011-2012 Vayavya Labs Pvt Ltd
12 #include <linux/clk-provider.h>
24 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
25 plat->has_gmac = 1; in common_default_data()
26 plat->force_sf_dma_mode = 1; in common_default_data()
28 plat->mdio_bus_data->needs_reset = true; in common_default_data()
30 /* Set default value for multicast hash bins */ in common_default_data()
31 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
33 /* Set default value for unicast filter entries */ in common_default_data()
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| D | dwmac-intel.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
56 return func_data->phy_addr; in stmmac_pci_find_phy_addr()
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| D | dwmac-loongson.c | 1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
85 plat->bus_id = pci_dev_id(pdev); in loongson_default_data()
87 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in loongson_default_data()
88 plat->has_gmac = 1; in loongson_default_data()
89 plat->force_sf_dma_mode = 1; in loongson_default_data()
91 /* Set default value for multicast hash bins */ in loongson_default_data()
92 plat->multicast_filter_bins = 256; in loongson_default_data()
94 plat->mac_interface = PHY_INTERFACE_MODE_NA; in loongson_default_data()
96 /* Set default value for unicast filter entries */ in loongson_default_data()
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | renesas,rzn1-gmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,rzn1-gmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Romain Gantois <romain.gantois@bootlin.com>
17 - renesas,r9a06g032-gmac
18 - renesas,rzn1-gmac
20 - compatible
23 - $ref: snps,dwmac.yaml#
28 - enum:
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| D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
23 - snps,dwmac
24 - snps,dwmac-3.40a
25 - snps,dwmac-3.50a
26 - snps,dwmac-3.610
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| D | starfive,jh7110-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
27 - items:
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| /linux-6.12.1/arch/arm64/boot/dts/intel/ |
| D | socfpga_agilex.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
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| /linux-6.12.1/arch/arm64/boot/dts/altera/ |
| D | socfpga_stratix10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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| /linux-6.12.1/arch/arm/boot/dts/renesas/ |
| D | r9a06g032.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
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| /linux-6.12.1/arch/arm/boot/dts/intel/socfpga/ |
| D | socfpga_arria10.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
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| D | socfpga.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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| /linux-6.12.1/drivers/net/ethernet/qlogic/qed/ |
| D | qed_l2.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
11 #include <linux/dma-mapping.h>
63 return -ENOMEM; in qed_l2_alloc()
64 p_hwfn->p_l2_info = p_l2_info; in qed_l2_alloc()
66 if (IS_PF(p_hwfn->cdev)) { in qed_l2_alloc()
67 p_l2_info->queues = RESC_NUM(p_hwfn, QED_L2_QUEUE); in qed_l2_alloc()
74 p_l2_info->queues = max_t(u8, rx, tx); in qed_l2_alloc()
77 pp_qids = kcalloc(p_l2_info->queues, sizeof(unsigned long *), in qed_l2_alloc()
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| D | qed_l2.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
85 /* MOVE is not supported for multicast */
192 u32 bins[8]; member
240 * Note At the moment - only used by non-linux VFs.
269 * @is_atomic: Hint from the caller - if the func can sleep or not.
298 * or remove arfs hw filter
332 /* 0-based queue index. Should reflect the relative qzone the
338 * - Producers would be placed in a different place.
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| /linux-6.12.1/arch/arc/boot/dts/ |
| D | axs10x_mb.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 interrupt-parent = <&mb_intc>;
20 creg_rst: reset-controller@11220 {
21 compatible = "snps,axs10x-reset";
22 #reset-cells = <1>;
27 compatible = "snps,axs10x-i2s-pll-clock";
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| D | hsdk.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/reset/snps,hsdk-reset.h>
18 #address-cells = <2>;
19 #size-cells = <2>;
22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
30 #address-cells = <1>;
31 #size-cells = <0>;
62 input_clk: input-clk {
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| /linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_sp.c | 3 * Copyright 2011-2013 Broadcom Corporation
10 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
38 * bnx2x_exe_queue_init - init the Exe Queue object
62 INIT_LIST_HEAD(&o->exe_queue); in bnx2x_exe_queue_init()
63 INIT_LIST_HEAD(&o->pending_comp); in bnx2x_exe_queue_init()
65 spin_lock_init(&o->lock); in bnx2x_exe_queue_init()
67 o->exe_chunk_len = exe_len; in bnx2x_exe_queue_init()
68 o->owner = owner; in bnx2x_exe_queue_init()
71 o->validate = validate; in bnx2x_exe_queue_init()
72 o->remove = remove; in bnx2x_exe_queue_init()
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| /linux-6.12.1/arch/riscv/boot/dts/starfive/ |
| D | jh7100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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| D | jh7110.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| /linux-6.12.1/drivers/net/wireless/ath/ath10k/ |
| D | wmi.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
29 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
45 * variable is already 4-byte aligned by virtue of being a u32
527 * for wmi_services is 64 as target is using only 4-bits of each 32-bit
533 __le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
534 BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
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| /linux-6.12.1/drivers/net/ethernet/mellanox/mlxsw/ |
| D | reg.h | 1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
72 /* SSPR - Switch System Port Record Register
73 * -----------------------------------------
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