Searched +full:mt8195 +full:- +full:pcie +full:- +full:phy (Results 1 – 7 of 7) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | mediatek,pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PCIe PHY
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
17 const: mediatek,mt8195-pcie-phy
22 reg-names:
24 - const: sif
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| D | mediatek,tphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
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| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | mediatek-pcie-gen3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
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| /linux-6.12.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8195.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
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| /linux-6.12.1/drivers/phy/mediatek/ |
| D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for the phy drivers.
6 obj-$(CONFIG_PHY_MTK_DP) += phy-mtk-dp.o
7 obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o
8 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
9 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
10 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
11 obj-$(CONFIG_PHY_MTK_XFI_TPHY) += phy-mtk-xfi-tphy.o
13 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
14 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
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| D | phy-mtk-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/nvmem-consumer.h>
11 #include <linux/phy/phy.h>
15 #include "phy-mtk-io.h"
36 * struct mtk_pcie_lane_efuse - eFuse data for each lane
50 * struct mtk_pcie_phy_data - phy data for each SoC
60 * struct mtk_pcie_phy - PCIe phy driver main structure
62 * @phy: pointer to generic phy
71 struct phy *phy; member
83 struct mtk_pcie_lane_efuse *data = &pcie_phy->efuse[lane]; in mtk_pcie_efuse_set_lane()
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| D | phy-mtk-tphy.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
18 #include <linux/phy/phy.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
29 /* u2 phy bank */
31 /* u3/pcie/sata phy banks */
35 /* version V2/V3 sub-banks offset base address */
37 /* u2 phy banks */
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