| /linux-6.12.1/drivers/clk/mstar/ |
| D | clk-msc313-mpll.c | 3 * MStar MSC313 MPLL driver
47 struct msc313_mpll *mpll = to_mpll(hw); in msc313_mpll_recalc_rate() local
51 regmap_field_read(mpll->input_div, &input_div); in msc313_mpll_recalc_rate()
52 regmap_field_read(mpll->output_div, &output_div); in msc313_mpll_recalc_rate()
53 regmap_field_read(mpll->loop_div_first, &loop_first); in msc313_mpll_recalc_rate()
54 regmap_field_read(mpll->loop_div_second, &loop_second); in msc313_mpll_recalc_rate()
74 struct msc313_mpll *mpll; in msc313_mpll_probe() local
82 mpll = devm_kzalloc(dev, sizeof(*mpll), GFP_KERNEL); in msc313_mpll_probe()
83 if (!mpll) in msc313_mpll_probe()
94 mpll->input_div = devm_regmap_field_alloc(dev, regmap, config1_input_div_first); in msc313_mpll_probe()
[all …]
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| D | Kconfig | 10 bool "MStar MPLL driver"
15 Support for the MPLL PLL and dividers block present on
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| /linux-6.12.1/drivers/clk/meson/ |
| D | clk-mpll.c | 9 * scaling capabilities. MPLL rates are calculated as:
19 #include "clk-mpll.h"
79 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_recalc_rate() local
83 sdm = meson_parm_read(clk->map, &mpll->sdm); in mpll_recalc_rate()
84 n2 = meson_parm_read(clk->map, &mpll->n2); in mpll_recalc_rate()
93 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_determine_rate() local
98 mpll->flags); in mpll_determine_rate()
113 struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk); in mpll_set_rate() local
117 params_from_rate(rate, parent_rate, &sdm, &n2, mpll->flags); in mpll_set_rate()
119 if (mpll->lock) in mpll_set_rate()
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | mstar,msc313-mpll.yaml | 4 $id: http://devicetree.org/schemas/clock/mstar,msc313-mpll.yaml#
7 title: MStar/Sigmastar MSC313 MPLL
13 The MStar/SigmaStar MSC313 and later ARMv7 chips have an MPLL block that
20 const: mstar,msc313-mpll
41 mpll@206000 {
42 compatible = "mstar,msc313-mpll";
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| D | mstar,msc313-cpupll.yaml | 39 #include <dt-bindings/clock/mstar-msc313-mpll.h>
44 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
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| D | sophgo,sg2042-clkgen.yaml | 28 - const: mpll
56 clock-names = "mpll",
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| D | mvebu-core-clock.txt | 38 3 = mpll (MPLL Clock)
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 72 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
78 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
112 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
187 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
219 if (mpll->reference_div < 2) in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
234 mpll->reference_freq = 1432; in radeon_get_clock_info()
239 mpll->reference_freq = 2700; in radeon_get_clock_info()
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/sigmastar/ |
| D | mstar-v7.dtsi | 9 #include <dt-bindings/clock/mstar-msc313-mpll.h>
153 mpll: mpll@206000 { label
154 compatible = "mstar,msc313-mpll";
164 clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
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| /linux-6.12.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 30 /* MPLL */
31 FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
32 FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
33 FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
34 FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
35 FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
103 "mpll" };
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| D | clk-mt7981-topckgen.c | 24 FACTOR(CLK_TOP_CB_M_416M, "cb_m_416m", "mpll", 1, 1),
25 FACTOR(CLK_TOP_CB_M_D2, "cb_m_d2", "mpll", 1, 2),
26 FACTOR(CLK_TOP_CB_M_D3, "cb_m_d3", "mpll", 1, 3),
27 FACTOR(CLK_TOP_M_D3_D2, "m_d3_d2", "mpll", 1, 2),
28 FACTOR(CLK_TOP_CB_M_D4, "cb_m_d4", "mpll", 1, 4),
29 FACTOR(CLK_TOP_CB_M_D8, "cb_m_d8", "mpll", 1, 8),
30 FACTOR(CLK_TOP_M_D8_D2, "m_d8_d2", "mpll", 1, 16),
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| D | clk-mt7988-topckgen.c | 28 FACTOR(CLK_TOP_MPLL_D2, "mpll_d2", "mpll", 1, 2),
29 FACTOR(CLK_TOP_MPLL_D3_D2, "mpll_d3_d2", "mpll", 1, 2),
30 FACTOR(CLK_TOP_MPLL_D4, "mpll_d4", "mpll", 1, 4),
31 FACTOR(CLK_TOP_MPLL_D8, "mpll_d8", "mpll", 1, 8),
32 FACTOR(CLK_TOP_MPLL_D8_D2, "mpll_d8_d2", "mpll", 1, 16),
62 "net1pll_d4", "net1pll_d5", "mpll" };
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 288 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
306 if (mpll) { in setPLL_double_lowregs()
322 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
326 if (mpll) { in setPLL_double_lowregs()
340 if (mpll) { in setPLL_double_lowregs()
349 if (mpll) { in setPLL_double_lowregs()
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| /linux-6.12.1/drivers/phy/qualcomm/ |
| D | phy-qcom-ipq806x-usb.c | 62 /* Override value for mpll */
105 /* MPLL bits */
125 u32 mpll; member
406 data |= SSPHY_MPLL(phy_dwc3->mpll); in qcom_ipq806x_usb_ss_phy_init()
532 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll)) in qcom_ipq806x_usb_phy_probe()
533 phy_dwc3->mpll = SSPHY_MPLL_VALUE; in qcom_ipq806x_usb_phy_probe()
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| /linux-6.12.1/drivers/clk/imx/ |
| D | clk-imx35.c | 64 /* 0 */ ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, enumerator
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
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| D | clk-imx27.c | 34 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
39 "ckih_gate", "mpll", "spll", "cpu_div",
46 static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
63 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
66 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); in _mx27_clocks_init()
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| D | clk-imx31.c | 33 static const char *mcu_main_sel[] = { "spll", "mpll", };
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
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| D | clk-imx25.c | 46 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
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| /linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_atomfirmware.c | 709 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atomfirmware_get_clock_info() local
768 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz); in amdgpu_atomfirmware_get_clock_info()
770 mpll->reference_div = 0; in amdgpu_atomfirmware_get_clock_info()
771 mpll->min_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
772 mpll->max_post_div = 1; in amdgpu_atomfirmware_get_clock_info()
773 mpll->min_ref_div = 2; in amdgpu_atomfirmware_get_clock_info()
774 mpll->max_ref_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
775 mpll->min_feedback_div = 4; in amdgpu_atomfirmware_get_clock_info()
776 mpll->max_feedback_div = 0xff; in amdgpu_atomfirmware_get_clock_info()
777 mpll->best_vco = 0; in amdgpu_atomfirmware_get_clock_info()
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| D | amdgpu_atombios.c | 571 struct amdgpu_pll *mpll = &adev->clock.mpll; in amdgpu_atombios_get_clock_info() local
643 mpll->reference_freq = in amdgpu_atombios_get_clock_info()
645 mpll->reference_div = 0; in amdgpu_atombios_get_clock_info()
647 mpll->pll_out_min = in amdgpu_atombios_get_clock_info()
649 mpll->pll_out_max = in amdgpu_atombios_get_clock_info()
653 if (mpll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
654 mpll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
656 mpll->pll_in_min = in amdgpu_atombios_get_clock_info()
658 mpll->pll_in_max = in amdgpu_atombios_get_clock_info()
666 mpll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/qcom/ |
| D | qcom-ipq8064-v2.0.dtsi | 62 qcom,mpll = <5>;
68 qcom,mpll = <5>;
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | qcom,ipq806x-usb-phy-ss.yaml | 49 qcom,mpll:
51 description: Override value for mpll.
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| /linux-6.12.1/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 191 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* 1600 MHz */
210 UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
217 "mpll/2", "spll/4", "mpll/3", "spll/3",
218 "spll/4", "spll/8", "mpll/4", "mpll/8"),
225 UNIPHIER_CLK_FACTOR("mpll", -1, "ref", 64, 1), /* Codec: 1600 MHz */
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| /linux-6.12.1/drivers/clk/mvebu/ |
| D | mv98dx3236.c | 24 * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
33 * SAR1[20:18] : CPU frequency DDR frequency MPLL frequency
94 { .id = MV98DX3236_CPU_TO_MPLL, .name = "mpll" },
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| /linux-6.12.1/arch/arm64/boot/dts/sprd/ |
| D | sharkl3.dtsi | 91 mpll: mpll@0 { label
92 compatible = "sprd,sc9863a-mpll";
|