| /linux-6.12.1/arch/powerpc/sysdev/ |
| D | mpic.c | 2 * arch/powerpc/kernel/mpic.c
5 * common implementation being IBM's MPIC. This driver also can deal
41 #include <asm/mpic.h>
44 #include "mpic.h"
53 .name = "mpic",
54 .dev_name = "mpic",
58 static struct mpic *mpics;
59 static struct mpic *mpic_primary;
72 [0] = { /* Original OpenPIC compatible MPIC */
152 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
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| D | fsl_mpic_err.c | 15 #include <asm/mpic.h>
17 #include "mpic.h"
36 struct mpic *mpic = irq_data_get_irq_chip_data(d); in fsl_mpic_mask_err() local
37 unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0]; in fsl_mpic_mask_err()
39 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR); in fsl_mpic_mask_err()
41 mpic_fsl_err_write(mpic->err_regs, eimr); in fsl_mpic_mask_err()
47 struct mpic *mpic = irq_data_get_irq_chip_data(d); in fsl_mpic_unmask_err() local
48 unsigned int src = virq_to_hw(d->irq) - mpic->err_int_vecs[0]; in fsl_mpic_unmask_err()
50 eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR); in fsl_mpic_unmask_err()
52 mpic_fsl_err_write(mpic->err_regs, eimr); in fsl_mpic_unmask_err()
[all …]
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| D | mpic.h | 10 extern void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq);
11 int __init mpic_msi_init_allocator(struct mpic *mpic);
12 int __init mpic_u3msi_init(struct mpic *mpic);
14 static inline void mpic_msi_reserve_hwirq(struct mpic *mpic, in mpic_msi_reserve_hwirq() argument
20 static inline int mpic_u3msi_init(struct mpic *mpic) in mpic_u3msi_init() argument
27 int __init mpic_pasemi_msi_init(struct mpic *mpic);
29 static inline int mpic_pasemi_msi_init(struct mpic *mpic) { return -1; } in mpic_pasemi_msi_init() argument
39 extern int mpic_map_error_int(struct mpic *mpic, unsigned int virq, irq_hw_number_t hw);
40 void __init mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum);
41 int __init mpic_setup_error_int(struct mpic *mpic, int intvec);
[all …]
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| D | mpic_msi.c | 11 #include <asm/mpic.h>
16 #include <sysdev/mpic.h>
18 void mpic_msi_reserve_hwirq(struct mpic *mpic, irq_hw_number_t hwirq) in mpic_msi_reserve_hwirq() argument
20 /* The mpic calls this even when there is no allocator setup */ in mpic_msi_reserve_hwirq()
21 if (!mpic->msi_bitmap.bitmap) in mpic_msi_reserve_hwirq()
24 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, hwirq); in mpic_msi_reserve_hwirq()
28 static int __init mpic_msi_reserve_u3_hwirqs(struct mpic *mpic) in mpic_msi_reserve_u3_hwirqs() argument
31 const struct irq_domain_ops *ops = mpic->irqhost->ops; in mpic_msi_reserve_u3_hwirqs()
36 pr_debug("mpic: found U3, guessing msi allocator setup\n"); in mpic_msi_reserve_u3_hwirqs()
45 msi_bitmap_reserve_hwirq(&mpic->msi_bitmap, i); in mpic_msi_reserve_u3_hwirqs()
[all …]
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-armada-370-xp.c | 69 * registers, which are relative to "mpic->base".
73 * "mpic->per_cpu". This base address points to a special address,
115 /* Registers relative to mpic->base */
125 /* Registers relative to mpic->per_cpu */
153 * struct mpic - MPIC private data structure
154 * @base: MPIC registers base address
156 * @parent_irq: parent IRQ if MPIC is not top-level interrupt controller
157 * @domain: MPIC main interrupt domain
170 struct mpic { struct
190 static struct mpic *mpic_data __ro_after_init; argument
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
| D | mpc8572ds.dtsi | 250 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
251 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
252 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
253 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
256 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
257 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
258 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
259 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
262 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
263 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | stxssa8555.dts | 69 interrupt-parent = <&mpic>;
75 interrupt-parent = <&mpic>;
84 interrupt-parent = <&mpic>;
95 interrupt-parent = <&mpic>;
111 interrupt-parent = <&mpic>;
119 interrupt-parent = <&mpic>;
127 interrupt-parent = <&mpic>;
135 interrupt-parent = <&mpic>;
151 interrupt-parent = <&mpic>;
162 interrupt-parent = <&mpic>;
[all …]
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| D | mvme5100.dts | 62 interrupt-parent = <&mpic>;
73 interrupt-parent = <&mpic>;
76 mpic: interrupt-controller@f3f80000 { label
98 interrupt-parent = <&mpic>;
112 0x5800 0x0 0x0 0x1 &mpic 0x0 0x2
113 0x5800 0x0 0x0 0x2 &mpic 0x0 0x2
114 0x5800 0x0 0x0 0x3 &mpic 0x0 0x2
115 0x5800 0x0 0x0 0x4 &mpic 0x0 0x2
120 0x6800 0x0 0x0 0x1 &mpic 0x5 0x1
121 0x6800 0x0 0x0 0x2 &mpic 0x6 0x1
[all …]
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| D | stx_gp3_8560.dts | 66 interrupt-parent = <&mpic>;
72 interrupt-parent = <&mpic>;
81 interrupt-parent = <&mpic>;
92 interrupt-parent = <&mpic>;
108 interrupt-parent = <&mpic>;
116 interrupt-parent = <&mpic>;
124 interrupt-parent = <&mpic>;
132 interrupt-parent = <&mpic>;
148 interrupt-parent = <&mpic>;
159 interrupt-parent = <&mpic>;
[all …]
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| D | storcenter.dts | 66 interrupt-parent = <&mpic>;
82 interrupt-parent = <&mpic>;
93 interrupt-parent = <&mpic>;
96 mpic: interrupt-controller@40000 { label
118 interrupt-parent = <&mpic>;
122 0x6800 0 0 1 &mpic 0 1
123 0x6800 0 0 2 &mpic 0 1
124 0x6800 0 0 3 &mpic 0 1
125 0x6800 0 0 4 &mpic 0 1
127 0x7000 0 0 1 &mpic 0 1
[all …]
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| D | tqm8548-bigflash.dts | 67 interrupt-parent = <&mpic>;
73 interrupt-parent = <&mpic>;
82 interrupt-parent = <&mpic>;
93 interrupt-parent = <&mpic>;
114 interrupt-parent = <&mpic>;
130 interrupt-parent = <&mpic>;
138 interrupt-parent = <&mpic>;
146 interrupt-parent = <&mpic>;
154 interrupt-parent = <&mpic>;
170 interrupt-parent = <&mpic>;
[all …]
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| D | tqm8548.dts | 67 interrupt-parent = <&mpic>;
73 interrupt-parent = <&mpic>;
82 interrupt-parent = <&mpic>;
93 interrupt-parent = <&mpic>;
114 interrupt-parent = <&mpic>;
130 interrupt-parent = <&mpic>;
138 interrupt-parent = <&mpic>;
146 interrupt-parent = <&mpic>;
154 interrupt-parent = <&mpic>;
170 interrupt-parent = <&mpic>;
[all …]
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| D | kuroboxHD.dts | 76 interrupt-parent = <&mpic>;
92 interrupt-parent = <&mpic>;
103 interrupt-parent = <&mpic>;
106 mpic: interrupt-controller@80040000 { label
126 interrupt-parent = <&mpic>;
130 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
131 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
135 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
[all …]
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| D | kuroboxHG.dts | 76 interrupt-parent = <&mpic>;
92 interrupt-parent = <&mpic>;
103 interrupt-parent = <&mpic>;
106 mpic: interrupt-controller@80040000 { label
126 interrupt-parent = <&mpic>;
130 0x5800 0x0 0x0 0x1 &mpic 0x0 0x1
131 0x5800 0x0 0x0 0x2 &mpic 0x1 0x1
132 0x5800 0x0 0x0 0x3 &mpic 0x2 0x1
133 0x5800 0x0 0x0 0x4 &mpic 0x3 0x1
135 0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
[all …]
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| D | tqm8540.dts | 68 interrupt-parent = <&mpic>;
74 interrupt-parent = <&mpic>;
83 interrupt-parent = <&mpic>;
94 interrupt-parent = <&mpic>;
120 interrupt-parent = <&mpic>;
128 interrupt-parent = <&mpic>;
136 interrupt-parent = <&mpic>;
144 interrupt-parent = <&mpic>;
160 interrupt-parent = <&mpic>;
170 interrupt-parent = <&mpic>;
[all …]
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| D | tqm8541.dts | 67 interrupt-parent = <&mpic>;
73 interrupt-parent = <&mpic>;
82 interrupt-parent = <&mpic>;
93 interrupt-parent = <&mpic>;
119 interrupt-parent = <&mpic>;
127 interrupt-parent = <&mpic>;
135 interrupt-parent = <&mpic>;
143 interrupt-parent = <&mpic>;
159 interrupt-parent = <&mpic>;
170 interrupt-parent = <&mpic>;
[all …]
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| D | tqm8555.dts | 67 interrupt-parent = <&mpic>;
73 interrupt-parent = <&mpic>;
82 interrupt-parent = <&mpic>;
93 interrupt-parent = <&mpic>;
119 interrupt-parent = <&mpic>;
127 interrupt-parent = <&mpic>;
135 interrupt-parent = <&mpic>;
143 interrupt-parent = <&mpic>;
159 interrupt-parent = <&mpic>;
170 interrupt-parent = <&mpic>;
[all …]
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| D | xpedite5330.dts | 105 interrupt-parent = <&mpic>;
210 interrupt-parent = <&mpic>;
216 interrupt-parent = <&mpic>;
223 interrupt-parent = <&mpic>;
232 interrupt-parent = <&mpic>;
243 interrupt-parent = <&mpic>;
317 interrupt-parent = <&mpic>;
333 interrupt-parent = <&mpic>;
341 interrupt-parent = <&mpic>;
349 interrupt-parent = <&mpic>;
[all …]
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| D | xcalibur1501.dts | 68 interrupt-parent = <&mpic>;
158 interrupt-parent = <&mpic>;
181 interrupt-parent = <&mpic>;
187 interrupt-parent = <&mpic>;
194 interrupt-parent = <&mpic>;
203 interrupt-parent = <&mpic>;
214 interrupt-parent = <&mpic>;
301 interrupt-parent = <&mpic>;
317 interrupt-parent = <&mpic>;
325 interrupt-parent = <&mpic>;
[all …]
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| D | xpedite5370.dts | 67 interrupt-parent = <&mpic>;
172 interrupt-parent = <&mpic>;
178 interrupt-parent = <&mpic>;
185 interrupt-parent = <&mpic>;
194 interrupt-parent = <&mpic>;
205 interrupt-parent = <&mpic>;
279 interrupt-parent = <&mpic>;
295 interrupt-parent = <&mpic>;
303 interrupt-parent = <&mpic>;
311 interrupt-parent = <&mpic>;
[all …]
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| D | xpedite5301.dts | 69 interrupt-parent = <&mpic>;
174 interrupt-parent = <&mpic>;
180 interrupt-parent = <&mpic>;
187 interrupt-parent = <&mpic>;
196 interrupt-parent = <&mpic>;
207 interrupt-parent = <&mpic>;
281 interrupt-parent = <&mpic>;
297 interrupt-parent = <&mpic>;
305 interrupt-parent = <&mpic>;
313 interrupt-parent = <&mpic>;
[all …]
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| /linux-6.12.1/arch/powerpc/include/asm/ |
| D | mpic.h | 25 /* On the FSL mpic implementations the Mode field is expand to be
122 * Tsi108 implementation of MPIC has many differences from the original one
176 /* weird mpic register indices and mask bits in the HW info array */
255 /* The instance data of a given MPIC */
256 struct mpic struct
258 /* The OpenFirmware dt node for this MPIC */
261 /* The remapper for this MPIC */
287 /* vector numbers used for FSL MPIC error interrupts */
302 /* The physical base address of the MPIC */
332 struct mpic *next; argument
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| /linux-6.12.1/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
17 Definition: Shall include "fsl,mpic". Freescale MPIC
20 0x10 in the MPIC.
51 MPIC must not be reset by the client program, and that
63 If present the MPIC will be assumed to be big-endian. Some
64 device-trees omit this property on MPIC nodes even when the MPIC is
70 If present the MPIC will be assumed to only be able to route
71 non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
112 MPIC a block of registers referred to as
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| D | mpic-msgr.txt | 1 * FSL MPIC Message Registers
4 representation of the message register blocks found in some FSL MPIC
11 "fsl,mpic-v<version>-msgr", where <version> is the version number of
12 the MPIC containing the message registers.
25 - mpic-msgr-receive-mask: Specifies what registers in the containing block
37 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
43 mpic-msgr-block0 = &mpic_msgr_block0;
44 mpic-msgr-block1 = &mpic_msgr_block1;
47 mpic_msgr_block0: mpic-msgr-block@41400 {
48 compatible = "fsl,mpic-v3.1-msgr";
[all …]
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| /linux-6.12.1/Documentation/virt/kvm/devices/ |
| D | mpic.rst | 4 MPIC interrupt controller
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
12 Only one MPIC instance, of any type, may be instantiated. The created
13 MPIC will act as the system interrupt controller, connecting to each
21 Base address of the 256 KiB MPIC register space. Must be
26 Access an MPIC register, as if the access were made from the guest.
27 "attr" is the byte offset into the MPIC register space. Accesses
46 The MPIC emulation supports IRQ routing. Only a single MPIC device can
53 The numbering is the same as the MPIC device tree binding -- based on
|