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/linux-6.12.1/Documentation/devicetree/bindings/arm/
Darm,vexpress-juno.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,vexpress-juno.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
11 - Linus Walleij <linus.walleij@linaro.org>
15 multicore Cortex-A class systems. The Versatile Express family contains both
18 The board consist of a motherboard and one or more daughterboards (tiles). The
19 motherboard provides a set of peripherals. Processor and RAM "live" on the
22 The motherboard and each core tile should be described by a separate Device
[all …]
Dvexpress-config.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Versatile Express configuration bus
10 - Andre Przywara <andre.przywara@arm.com>
14 platform's configuration bus via "system control" interface, addressing
16 function and device numbers - see motherboard's TRM for more details.
20 const: arm,vexpress,config-bus
22 arm,vexpress,config-bridge:
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/linux-6.12.1/arch/arm64/boot/dts/arm/
Drtsm_ve-motherboard-rs2.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * "rs2" extension for the v2m motherboard
8 bus@8000000 {
9 motherboard-bus@8000000 {
10 arm,v2m-memory-map = "rs2";
12 iofpga-bus@300000000 {
Drtsm_ve-motherboard.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * Motherboard component
11 v2m_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "v2m:clk24mhz";
18 v2m_refclk1mhz: clock-1000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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Djuno-motherboard.dtsi2 * ARM Juno Platform motherboard peripherals
4 * Copyright (c) 2013-2014 ARM Ltd
11 mb_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "juno_mb:clk24mhz";
18 mb_clk25mhz: clock-25000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/linux-6.12.1/Documentation/PCI/
Dacpi-info.rst1 .. SPDX-License-Identifier: GPL-2.0
39 If the OS is expected to manage a non-discoverable device described via
46 they forward down to the PCI bus, as well as registers of the host bridge
48 things like secondary/subordinate bus registers that determine the bus
50 These are all device-specific, non-architected things, so the only way a
52 the device-specific details. The host bridge registers also include ECAM
66 bridge registers (including ECAM space) in PNP0C02 catch-all devices [6].
67 With the exception of ECAM, the bridge register space is device-specific
78 PNP0C02 "motherboard" devices are basically a catch-all. There's no
89 the address space is device-specific. An ACPI OS learns the base address
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/linux-6.12.1/Documentation/i2c/busses/
Di2c-via.rst2 Kernel driver i2c-via
12 -----------
14 i2c-via is an i2c bus driver for motherboards with VIA chipset.
17 - MVP3, VP3, VP2/97, VPX/97
18 - others with South bridge VT82C586B
25 ---------
28 You have VT82C586B on the motherboard, but not in the listing.
39 datasheets, but there are several ways the motherboard manufacturer
Di2c-ali15x3.rst2 Kernel driver i2c-ali15x3
12 - Frodo Looijaard <frodol@dds.nl>,
13 - Philip Edelbrock <phil@netroedge.com>,
14 - Mark D. Studebaker <mdsxyz123@yahoo.com>
17 -----------------
24 -----
33 modprobe i2c-ali15x3 force_addr=0xe800
40 -----------
52 100MHz CPU Front Side bus
54 CPU Front Side bus
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Di2c-piix4.rst2 Kernel driver i2c-piix4
9 * ServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
18 * AMD Hudson-2, ML, CZ
26 - Frodo Looijaard <frodol@dds.nl>
27 - Philip Edelbrock <phil@netroedge.com>
31 -----------------
40 -----------
43 functionality. Among other things, it implements the PCI bus. One of its
44 minor functions is implementing a System Management Bus. This is a true
45 SMBus - you can not access it on I2C levels. The good news is that it
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Di2c-i801.rst2 Kernel driver i2c-i801
7 * Intel 82801AA and 82801AB (ICH and ICH0 - part of the
9 * Intel 82801BA (ICH2 - part of the '815E' chipset)
59 - Mark Studebaker <mdsxyz123@yahoo.com>
60 - Jean Delvare <jdelvare@suse.de>
64 -----------------
82 -----------
86 Intel's '810' chipset for Celeron-based PCs, '810E' chipset for
87 Pentium-based PCs, '815E' chipset, and others.
107 --------------------
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/linux-6.12.1/arch/arm/boot/dts/arm/
Dvexpress-v2m.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Motherboard Express uATX
6 * V2M-P1
8 * HBI-0190D
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 bus@40000000 {
24 compatible = "simple-bus";
25 #address-cells = <1>;
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Dvexpress-v2m-rs1.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Motherboard Express uATX
6 * V2M-P1
8 * HBI-0190D
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 v2m_fixed_3v3: regulator-3v3 {
24 compatible = "regulator-fixed";
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/linux-6.12.1/Documentation/hwmon/
Dw83793.rst10 Addresses scanned: I2C 0x2c - 0x2f
15 - Yuan Mu (Winbond Electronics)
16 - Rudolf Marek <r.marek@assembler.cz>
20 -----------------
25 This parameter is not recommended, it will lose motherboard specific
28 * force_subclients=bus,caddr,saddr1,saddr2
31 to force the subclients of chip 0x2f on bus 0 to i2c addresses
36 -----------
44 sets of 6-pin CPU VID input.
47 If your motherboard maker used the reference design, the resolution of
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Dvia686a.rst10 Addresses scanned: ISA in PCI-space encoded address
12 Datasheet: On request through web form (http://www.via.com.tw/en/resources/download-center/)
15 - Kyösti Mälkki <kmalkki@cc.hut.fi>,
16 - Mark D. Studebaker <mdsxyz123@yahoo.com>
17 - Bob Dougherty <bobd@stanford.edu>
18 - (Some conversion-factor data were contributed by
19 - Jonathan Teh Soon Yew <j.teh@iname.com>
20 - and Alex van Kaam <darkside@chello.nl>.)
23 -----------------
36 -----------
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/linux-6.12.1/arch/m68k/
DKconfig.bus1 # SPDX-License-Identifier: GPL-2.0
4 comment "Bus Support"
7 bool "DIO bus support"
11 Say Y here to enable support for the "DIO" expansion bus used in
21 bool "Amiga Zorro (AutoConfig) bus support"
24 This enables support for the Zorro bus in the Amiga. If you have
43 Find out whether you have ISA slots on your motherboard. ISA is the
44 name of a bus system, i.e. the way the CPU talks to the other stuff
45 inside your box. Other bus systems are PCI, EISA, MicroChannel
/linux-6.12.1/arch/mips/pci/
Dpci-generic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * addresses to be allocated in the 0x000-0x0ff region
18 * the low 10 bits of the IO address. The 0x00-0xff region
19 * is reserved for motherboard devices that decode all 16
20 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
21 * but we want to try to avoid allocating at 0x2900-0x2bff
22 * which might have be mirrored at 0x0100-0x03ff..
28 resource_size_t start = res->start; in pcibios_align_resource()
31 if (res->flags & IORESOURCE_IO && start & 0x300) in pcibios_align_resource()
34 start = (start + align - 1) & ~(align - 1); in pcibios_align_resource()
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Dpci-legacy.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
6 * written by Ralf Baechle (ralf@linux-mips.org)
18 #include <asm/cpu-info.h>
35 * addresses to be allocated in the 0x000-0x0ff region
39 * the low 10 bits of the IO address. The 0x00-0xff region
40 * is reserved for motherboard devices that decode all 16
41 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
42 * but we want to try to avoid allocating at 0x2900-0x2bff
43 * which might have be mirrored at 0x0100-0x03ff..
[all …]
/linux-6.12.1/arch/x86/pci/
Dmmconfig-shared.c1 // SPDX-License-Identifier: GPL-2.0
3 * Low-level direct PCI config space access via ECAM - common code between
4 * i386 and x86-64.
7 * - known chipset handling
8 * - ACPI decoding and validation
10 * Per-architecture code takes care of the mappings and accesses
39 if (cfg->res.parent) in pci_mmconfig_remove()
40 release_resource(&cfg->res); in pci_mmconfig_remove()
41 list_del(&cfg->list); in pci_mmconfig_remove()
58 /* keep list sorted by segment and starting bus number */ in list_add_sorted()
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/linux-6.12.1/arch/xtensa/kernel/
Dpci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * PCI bios-type initialisation for PCI machines
7 * Copyright (C) 2001-2005 Tensilica Inc.
24 #include <asm/pci-bridge.h>
30 * addresses to be allocated in the 0x000-0x0ff region
34 * the low 10 bits of the IO address. The 0x00-0xff region
35 * is reserved for motherboard devices that decode all 16
36 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
37 * but we want to try to avoid allocating at 0x2900-0x2bff
38 * which might have be mirrored at 0x0100-0x03ff..
[all …]
/linux-6.12.1/arch/m68k/kernel/
Dpcibios.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pci.c -- basic PCI support code
15 * From arch/i386/kernel/pci-i386.c:
19 * addresses to be allocated in the 0x000-0x0ff region
23 * the low 10 bits of the IO address. The 0x00-0xff region
24 * is reserved for motherboard devices that decode all 16
25 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
26 * but we want to try to avoid allocating at 0x2900-0x2bff
27 * which might be mirrored at 0x0100-0x03ff..
32 resource_size_t start = res->start; in pcibios_align_resource()
[all …]
/linux-6.12.1/drivers/pci/pcie/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 # PCI Express Port Bus Configuration
6 bool "PCI Express Port Bus support"
9 This enables PCI Express Port Bus support. Users can then enable
10 support for Native Hot-Plug, Advanced Error Reporting, Power
21 Say Y here if you have a motherboard that supports PCIe native
46 to trigger various real hardware errors. Software-based
48 help of a user space helper tool aer-inject, which can be
50 https://github.com/intel/aer-inject.git
69 (transaction layer end-to-end CRC checking).
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/linux-6.12.1/drivers/gpu/drm/pl111/
Dpl111_versatile.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * This is based on code and know-how in the previous frame buffer
6 * driver in drivers/video/fbdev/amba-clcd.c:
46 .compatible = "arm,core-module-integrator",
50 .compatible = "arm,versatile-sysreg",
54 .compatible = "arm,realview-eb-syscon",
58 .compatible = "arm,realview-pb1176-syscon",
62 .compatible = "arm,realview-pb11mp-syscon",
66 .compatible = "arm,realview-pba8-syscon",
70 .compatible = "arm,realview-pbx-syscon",
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/linux-6.12.1/drivers/char/agp/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
7 AGP (Accelerated Graphics Port) is a bus system mainly used to
12 as a sort of "AGP driver" for the motherboard's chipset.
20 write-combining with MTRR support on the AGP bus. Without it, OpenGL
37 For the ALi-chipset question, ALi suggests you refer to
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
64 X using the on-CPU northbridge of the AMD Athlon64/Opteron CPUs.
117 AGP bus adapter on HP PA-RISC machines (Ok, just on the C8000
/linux-6.12.1/arch/alpha/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
43 The Alpha is a 64-bit general-purpose processor designed and
45 now Hewlett-Packard. The Alpha Linux project has a home page at
92 Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
94 LX164 AlphaPC164-LX
101 Ruffian RPX164-2, AlphaPC164-UX, AlphaPC164-BX
102 SX164 AlphaPC164-SX
119 bool "Alcor/Alpha-XLT"
122 For systems using the Digital ALCOR chipset: 5 chips (4, 64-bit data
123 slices (Data Switch, DSW) - 208-pin PQFP and 1 control (Control, I/O
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