Home
last modified time | relevance | path

Searched full:mw (Results 1 – 25 of 178) sorted by relevance

12345678

/linux-6.12.1/drivers/infiniband/sw/rxe/
Drxe_mw.c18 struct rxe_mw *mw = to_rmw(ibmw); in rxe_alloc_mw() local
25 ret = rxe_add_to_pool(&rxe->mw_pool, mw); in rxe_alloc_mw()
31 mw->rkey = ibmw->rkey = (mw->elem.index << 8) | rxe_get_next_key(-1); in rxe_alloc_mw()
32 mw->state = (mw->ibmw.type == IB_MW_TYPE_2) ? in rxe_alloc_mw()
34 spin_lock_init(&mw->lock); in rxe_alloc_mw()
36 rxe_finalize(mw); in rxe_alloc_mw()
43 struct rxe_mw *mw = to_rmw(ibmw); in rxe_dealloc_mw() local
45 rxe_cleanup(mw); in rxe_dealloc_mw()
51 struct rxe_mw *mw, struct rxe_mr *mr, int access) in rxe_check_bind_mw() argument
53 if (mw->ibmw.type == IB_MW_TYPE_1) { in rxe_check_bind_mw()
[all …]
Drxe.h58 #define rxe_dbg_mw(mw, fmt, ...) ibdev_dbg((mw)->ibmw.device, \ argument
59 "mw#%d %s: " fmt, (mw)->elem.index, __func__, ##__VA_ARGS__)
79 #define rxe_err_mw(mw, fmt, ...) ibdev_err_ratelimited((mw)->ibmw.device, \ argument
80 "mw#%d %s: " fmt, (mw)->elem.index, __func__, ##__VA_ARGS__)
100 #define rxe_info_mw(mw, fmt, ...) ibdev_info_ratelimited((mw)->ibmw.device, \ argument
101 "mw#%d %s: " fmt, (mw)->elem.index, __func__, ##__VA_ARGS__)
Drxe_resp.c434 struct rxe_mw *mw = NULL; in check_rkey() local
486 mw = rxe_lookup_mw(qp, access, rkey); in check_rkey()
487 if (!mw) { in check_rkey()
488 rxe_dbg_qp(qp, "no MW matches rkey %#x\n", rkey); in check_rkey()
493 mr = mw->mr; in check_rkey()
495 rxe_dbg_qp(qp, "MW doesn't have an MR\n"); in check_rkey()
500 if (mw->access & IB_ZERO_BASED) in check_rkey()
501 qp->resp.offset = mw->addr; in check_rkey()
504 rxe_put(mw); in check_rkey()
505 mw = NULL; in check_rkey()
[all …]
Drxe_verbs.h454 static inline struct rxe_mw *to_rmw(struct ib_mw *mw) in to_rmw() argument
456 return mw ? container_of(mw, struct rxe_mw, ibmw) : NULL; in to_rmw()
469 static inline struct rxe_pd *rxe_mw_pd(struct rxe_mw *mw) in rxe_mw_pd() argument
471 return to_rpd(mw->ibmw.pd); in rxe_mw_pd()
/linux-6.12.1/drivers/platform/x86/amd/pmf/
Dauto-mode.c36 pr_debug("pfloor_perf: %u mW\n", data->mode_set[AUTO_PERFORMANCE].power_floor); in amd_pmf_dump_auto_mode_defaults()
37 pr_debug("pfloor_balanced: %u mW\n", data->mode_set[AUTO_BALANCE].power_floor); in amd_pmf_dump_auto_mode_defaults()
38 pr_debug("pfloor_quiet: %u mW\n", data->mode_set[AUTO_QUIET].power_floor); in amd_pmf_dump_auto_mode_defaults()
41 pr_debug("pd_balanced_to_perf: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
43 pr_debug("pd_perf_to_balanced: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
45 pr_debug("pd_quiet_to_balanced: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
47 pr_debug("pd_balanced_to_quiet: %u mW\n", in amd_pmf_dump_auto_mode_defaults()
56 pr_debug("stt_min_limit_perf_on_lap: %u mW\n", its_mode->power_control.stt_min); in amd_pmf_dump_auto_mode_defaults()
61 pr_debug("stt_min_limit_perf: %u mW\n", its_mode->power_control.stt_min); in amd_pmf_dump_auto_mode_defaults()
66 pr_debug("stt_min_limit_balanced: %u mW\n", its_mode->power_control.stt_min); in amd_pmf_dump_auto_mode_defaults()
[all …]
Dpmf.h203 u16 core_power[16]; /* mW */
207 u16 stapm_opn_limit; /* mW */
208 u16 stapm_cur_limit; /* mW */
224 u16 ipu_power; /* mW */
225 u32 apu_power; /* mW */
226 u32 gfx_power; /* mW */
227 u32 dgpu_power; /* mW */
228 u32 socket_power; /* mW */
229 u32 all_core_power; /* mW */
259 u16 power[2];/* in mW */
[all …]
Dcnqf.c51 pr_debug("pfloor_%s: %u mW\n", state_as_str_cnqf(i), data->ps[i].pfloor); in amd_pmf_cnqf_dump_defaults()
52 pr_debug("fppt_%s: %u mW\n", state_as_str_cnqf(i), data->ps[i].fppt); in amd_pmf_cnqf_dump_defaults()
53 pr_debug("sppt_%s: %u mW\n", state_as_str_cnqf(i), data->ps[i].sppt); in amd_pmf_cnqf_dump_defaults()
54 pr_debug("sppt_apuonly_%s: %u mW\n", in amd_pmf_cnqf_dump_defaults()
56 pr_debug("spl_%s: %u mW\n", state_as_str_cnqf(i), data->ps[i].spl); in amd_pmf_cnqf_dump_defaults()
57 pr_debug("stt_minlimit_%s: %u mW\n", in amd_pmf_cnqf_dump_defaults()
181 dev_dbg(dev->dev, "avg_power: %u mW total_power: %u mW count: %u timer: %u ms\n", in amd_pmf_trans_cnqf()
203 dev_dbg(dev->dev, "[CNQF] Avg power: %u mW socket power: %u mW mode:%s\n", in amd_pmf_trans_cnqf()
/linux-6.12.1/Documentation/power/powercap/
Ddtpm.rst56 SoC (400mW - 3100mW)
58 `-- pkg (400mW - 3100mW)
60 |-- pd0 (100mW - 700mW)
62 `-- pd1 (300mW - 2400mW)
66 SoC (600mW - 5900mW)
68 |-- pkg (400mW - 3100mW)
70 | |-- pd0 (100mW - 700mW)
72 | `-- pd1 (300mW - 2400mW)
74 `-- pd2 (200mW - 2800mW)
90 …dren given their weights. For example, if we set a power limitation of 3200mW at the 'SoC' root no…
[all …]
/linux-6.12.1/net/netfilter/ipvs/
Dip_vs_wrr.c28 * - mw: maximum weight
31 * As result, all weights are in the [di..mw] range with a step=di.
33 * First, we start with cw = mw and select dests with weight >= cw.
35 * Last pass should be with cw = di. We have mw/di passes in total:
47 * So, we modify how mw is calculated, now it is reduced with (di - 1),
63 int mw; /* maximum weight */ member
119 mark->mw = ip_vs_wrr_max_weight(svc) - (mark->di - 1); in ip_vs_wrr_init_svc()
120 mark->cw = mark->mw; in ip_vs_wrr_init_svc()
146 mark->mw = ip_vs_wrr_max_weight(svc) - (mark->di - 1); in ip_vs_wrr_dest_changed()
147 if (mark->cw > mark->mw || !mark->cw) in ip_vs_wrr_dest_changed()
[all …]
/linux-6.12.1/drivers/ntb/
Dntb_transport.c619 struct ntb_transport_mw *mw; in ntb_transport_setup_qp_mw() local
631 mw = &nt->mw_vec[mw_num]; in ntb_transport_setup_qp_mw()
633 if (!mw->virt_addr) in ntb_transport_setup_qp_mw()
641 rx_size = (unsigned int)mw->xlat_size / num_qps_mw; in ntb_transport_setup_qp_mw()
642 qp->rx_buff = mw->virt_addr + rx_size * (qp_num / mw_count); in ntb_transport_setup_qp_mw()
795 struct ntb_transport_mw *mw = &nt->mw_vec[num_mw]; in ntb_free_mw() local
798 if (!mw->virt_addr) in ntb_free_mw()
802 dma_free_coherent(&pdev->dev, mw->alloc_size, in ntb_free_mw()
803 mw->alloc_addr, mw->dma_addr); in ntb_free_mw()
804 mw->xlat_size = 0; in ntb_free_mw()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu14_driver_if_v14_0_0.h179 uint16_t CorePower[16]; //CAC calculated core power [mW]
183 uint16_t StapmOpnLimit; //Maximum IRM defined STAPM power limit [mW]
184 uint16_t StapmCurrentLimit; //Time filtered STAPM power limit [mW]
200 uint16_t IpuPower; //Time filtered IPU power [mW]
201 uint32_t ApuPower; //Time filtered APU power [mW]
202 uint32_t GfxPower; //Time filtered GFX power [mW]
203 uint32_t dGpuPower; //Time filtered dGPU power [mW]
204 uint32_t SocketPower; //Time filtered power used for PPT/STAPM [APU+dGPU] [mW]
205 …t AllCorePower; //Time filtered sum of core power across all cores in the socket [mW]
219 uint16_t Psys; //Time filtered Psys power [mW]
Dsmu13_driver_if_yellow_carp.h171 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
175 uint16_t CorePower[8]; //[mW]
184 uint16_t CurrentSocketPower; //[mW]
187 uint32_t ApuPower; //[mW]
188 uint32_t dGpuPower; //[mW]
Dsmu11_driver_if_vangogh.h180 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
181 uint16_t CurrentSocketPower; //[mW]
185 uint16_t CorePower[8]; //[mW]
210 uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
211 uint16_t CurrentSocketPower; //[mW]
215 uint16_t CorePower[4]; //[mW]
Dsmu11_driver_if_cyan_skillfish.h42 uint32_t CorePower[6]; //[mW]
61 uint32_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_GFX
62 uint32_t CurrentSocketPower; //[mW]
Dsmu13_driver_if_v13_0_4.h171 uint16_t Power[2]; //[mW] indices: VDDCR_VDD, VDDCR_SOC
175 uint16_t CorePower[8]; //[mW]
184 uint16_t CurrentSocketPower; //[mW]
187 uint32_t ApuPower; //[mW]
188 uint32_t dGpuPower; //[mW]
/linux-6.12.1/drivers/infiniband/hw/hns/
Dhns_roce_mr.c484 struct hns_roce_mw *mw) in hns_roce_mw_free() argument
489 if (mw->enabled) { in hns_roce_mw_free()
491 key_to_hw_index(mw->rkey) & in hns_roce_mw_free()
494 dev_warn(dev, "MW DESTROY_MPT failed (%d)\n", ret); in hns_roce_mw_free()
497 key_to_hw_index(mw->rkey)); in hns_roce_mw_free()
501 (int)key_to_hw_index(mw->rkey)); in hns_roce_mw_free()
505 struct hns_roce_mw *mw) in hns_roce_mw_enable() argument
510 unsigned long mtpt_idx = key_to_hw_index(mw->rkey); in hns_roce_mw_enable()
524 ret = hr_dev->hw->mw_write_mtpt(mailbox->buf, mw); in hns_roce_mw_enable()
526 dev_err(dev, "MW write mtpt fail!\n"); in hns_roce_mw_enable()
[all …]
/linux-6.12.1/drivers/net/ethernet/mellanox/mlx4/
Dmr.c815 struct mlx4_mw *mw) in mlx4_mw_alloc() argument
829 mw->key = hw_index_to_key(index); in mlx4_mw_alloc()
830 mw->pd = pd; in mlx4_mw_alloc()
831 mw->type = type; in mlx4_mw_alloc()
832 mw->enabled = MLX4_MPT_DISABLED; in mlx4_mw_alloc()
838 int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw) in mlx4_mw_enable() argument
844 err = mlx4_mpt_alloc_icm(dev, key_to_hw_index(mw->key)); in mlx4_mw_enable()
858 mpt_entry->key = cpu_to_be32(key_to_hw_index(mw->key)); in mlx4_mw_enable()
859 mpt_entry->pd_flags = cpu_to_be32(mw->pd); in mlx4_mw_enable()
860 if (mw->type == MLX4_MW_TYPE_2) { in mlx4_mw_enable()
[all …]
/linux-6.12.1/include/uapi/linux/
Dpsp-dbc.h121 * @PARAM_GET_PWR_CAP: Get socket power cap (mW)
122 * @PARAM_SET_PWR_CAP: Set socket power cap (mW)
128 * @PARAM_GET_SOC_PWR_MAX: Get maximum allowed value for SoC power (mw)
129 * @PARAM_GET_SOC_PWR_MIN: Get minimum allowed value for SoC power (mw)
130 * @PARAM_GET_SOC_PWR_CUR: Get current value for SoC Power (mW)
/linux-6.12.1/fs/ocfs2/
Ddlmglue.c434 struct ocfs2_mask_waiter *mw, int ret) in ocfs2_update_lock_stats() argument
447 kt = ktime_sub(ktime_get(), mw->mw_lock_start); in ocfs2_update_lock_stats()
474 struct ocfs2_mask_waiter *mw; in ocfs2_track_lock_wait() local
481 mw = list_first_entry(&lockres->l_mask_waiters, in ocfs2_track_lock_wait()
484 ktime_to_us(ktime_mono_to_real(mw->mw_lock_start)); in ocfs2_track_lock_wait()
487 static inline void ocfs2_init_start_time(struct ocfs2_mask_waiter *mw) in ocfs2_init_start_time() argument
489 mw->mw_lock_start = ktime_get(); in ocfs2_init_start_time()
496 int level, struct ocfs2_mask_waiter *mw, int ret) in ocfs2_update_lock_stats() argument
505 static inline void ocfs2_init_start_time(struct ocfs2_mask_waiter *mw) in ocfs2_init_start_time() argument
891 struct ocfs2_mask_waiter *mw, *tmp; in lockres_set_flags() local
[all …]
/linux-6.12.1/include/linux/usb/
Dpd.h246 #define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
250 #define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) argument
372 #define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */
373 #define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
375 #define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT) argument
376 #define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT) argument
498 #define PD_P_SNK_STDBY_MW 2500 /* 2500 mW */
/linux-6.12.1/Documentation/hwmon/
Dltc4245.rst86 power1_input 12v power usage (mW)
87 power2_input 5v power usage (mW)
88 power3_input 3v power usage (mW)
89 power4_input Vee (-12v) power usage (mW)
/linux-6.12.1/drivers/clk/rockchip/
Dclk.h603 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\ argument
614 .mux_width = mw, \
624 #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ argument
635 .mux_width = mw, \
683 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \ argument
694 .mux_width = mw, \
701 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \ argument
712 .mux_width = mw, \
721 mw, mf, ds, dw, df, dt) \ argument
731 .mux_width = mw, \
[all …]
/linux-6.12.1/drivers/net/ethernet/marvell/octeontx2/af/
Drvu.c33 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
2195 struct mbox_wq_info *mw; in __rvu_mbox_handler() local
2200 mw = &rvu->afpf_wq_info; in __rvu_mbox_handler()
2203 mw = &rvu->afvf_wq_info; in __rvu_mbox_handler()
2209 devid = mwork - mw->mbox_wrk; in __rvu_mbox_handler()
2210 mbox = &mw->mbox; in __rvu_mbox_handler()
2215 if (mw->mbox_wrk[devid].num_msgs == 0) in __rvu_mbox_handler()
2220 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) { in __rvu_mbox_handler()
2253 mw->mbox_wrk[devid].num_msgs = 0; in __rvu_mbox_handler()
2285 struct mbox_wq_info *mw; in __rvu_mbox_up_handler() local
[all …]
/linux-6.12.1/arch/mips/txx9/generic/
Dmem_tx4927.c46 unsigned int mw = 0; in tx4927_process_sdccr() local
61 mw = 8 >> sdccr_mw; in tx4927_process_sdccr()
64 return rs * cs * mw * bs; in tx4927_process_sdccr()
/linux-6.12.1/Documentation/driver-api/
Dntb.rst52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
68 | dma-mapped | | | MW base addr |<== memory-mapped IO
70 | (addr) |<===================| MW xlat addr |<-ntb_peer_mw_set_trans(addr)
246 starts from the first mw idx, and a negative value starts from the last
247 mw idx. Both sides MUST set the same value here! The default value is

12345678