Searched +full:ls1028a +full:- +full:enetc +full:- +full:ierb (Results 1 – 5 of 5) sorted by relevance
/linux-6.12.1/Documentation/devicetree/bindings/net/ |
D | fsl,enetc-ierb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/net/fsl,enetc-ierb.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 which preconfigures the FIFO limits for the ENETC ports. 14 - Frank Li <Frank.Li@nxp.com> 15 - Vladimir Oltean <vladimir.oltean@nxp.com> 16 - Wei Fang <wei.fang@nxp.com> 17 - Claudiu Manoil <claudiu.manoil@nxp.com> 22 - fsl,ls1028a-enetc-ierb [all …]
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/linux-6.12.1/drivers/net/ethernet/freescale/enetc/ |
D | enetc_ierb.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 4 * The Integrated Endpoint Register Block (IERB) is configured by pre-boot 5 * software and is supposed to be to ENETC what a NVRAM is to a 'real' PCIe 6 * card. Upon FLR, values from the IERB are transferred to the ENETC PFs, and 7 * are read-only in the PF memory space. 9 * This driver fixes up the power-on reset values for the ENETC shared FIFO, 25 #include "enetc.h" 28 /* IERB registers */ 42 static void enetc_ierb_write(struct enetc_ierb *ierb, u32 offset, u32 val) in enetc_ierb_write() argument 44 iowrite32(val, ierb->regs + offset); in enetc_ierb_write() [all …]
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D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 6 drivers for the NXP ENETC controller. 8 If compiled as module (M), the module name is fsl-enetc-core. 11 tristate "ENETC PF driver" 21 This driver supports NXP ENETC gigabit ethernet controller PCIe 22 physical function (PF) devices, managing ENETC Ports at a privileged 25 If compiled as module (M), the module name is fsl-enetc. 28 tristate "ENETC VF driver" 35 This driver supports NXP ENETC gigabit ethernet controller PCIe 36 virtual function (VF) devices enabled by the ENETC PF driver. [all …]
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D | enetc_pf.c | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* Copyright 2017-2019 NXP */ 11 #include <linux/pcs-lynx.h> 15 #define ENETC_DRV_NAME_STR "ENETC PF driver" 19 u32 upper = __raw_readl(hw->port + ENETC_PSIPMAR0(si)); in enetc_pf_get_primary_mac_addr() 20 u16 lower = __raw_readw(hw->port + ENETC_PSIPMAR1(si)); in enetc_pf_get_primary_mac_addr() 32 __raw_writel(upper, hw->port + ENETC_PSIPMAR0(si)); in enetc_pf_set_primary_mac_addr() 33 __raw_writew(lower, hw->port + ENETC_PSIPMAR1(si)); in enetc_pf_set_primary_mac_addr() 41 if (!is_valid_ether_addr(saddr->sa_data)) in enetc_pf_set_mac_addr() 42 return -EADDRNOTAVAIL; in enetc_pf_set_mac_addr() [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | fsl-ls1028a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 5 * Copyright 2018-2020 NXP 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 16 compatible = "fsl,ls1028a"; 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; [all …]
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