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Searched +full:lpc3220 +full:- +full:adc (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/iio/adc/
Dnxp,lpc3220-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,lpc3220-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP LPC3220 SoC ADC controller
10 - Gregory Clement <gregory.clement@bootlin.com>
17 const: nxp,lpc3220-adc
25 vref-supply: true
27 "#io-channel-cells":
31 - compatible
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dnxp,lpc3220-mic.txt4 - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic".
5 - reg: should contain IC registers location and length.
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
10 IRQ_TYPE_EDGE_RISING = low-to-high edge triggered,
11 IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered,
12 IRQ_TYPE_LEVEL_HIGH = active high level-sensitive,
13 IRQ_TYPE_LEVEL_LOW = active low level-sensitive.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
23 mic: interrupt-controller@40008000 {
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/linux-6.12.1/arch/arm/boot/dts/nxp/lpc/
Dlpc32xx.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
9 #include <dt-bindings/clock/lpc32xx-clock.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "nxp,lpc3220";
16 interrupt-parent = <&mic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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Dlpc18xx.dtsi9 * Released under the terms of 3-clause BSD License
14 #include "../../armv7-m.dtsi"
16 #include "dt-bindings/clock/lpc18xx-cgu.h"
17 #include "dt-bindings/clock/lpc18xx-ccu.h"
23 #address-cells = <1>;
24 #size-cells = <1>;
27 #address-cells = <1>;
28 #size-cells = <0>;
31 compatible = "arm,cortex-m3";
40 compatible = "fixed-clock";
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/linux-6.12.1/Documentation/devicetree/bindings/input/touchscreen/
Dlpc32xx-tsc.txt4 - compatible: must be "nxp,lpc3220-tsc"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: The TSC/ADC interrupt
12 compatible = "nxp,lpc3220-tsc";
14 interrupt-parent = <&mic>;
/linux-6.12.1/drivers/iio/adc/
Dlpc32xx_adc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * lpc32xx_adc.c - Support for ADC in LPC32XX
5 * 3-channel, 10-bit ADC
46 #define LPC32XXAD_NAME "lpc32xx-adc"
70 mutex_lock(&st->lock); in lpc32xx_read_raw()
71 ret = clk_prepare_enable(st->clk); in lpc32xx_read_raw()
73 mutex_unlock(&st->lock); in lpc32xx_read_raw()
77 __raw_writel(LPC32XXAD_INTERNAL | (chan->address) | in lpc32xx_read_raw()
79 LPC32XXAD_SELECT(st->adc_base)); in lpc32xx_read_raw()
82 LPC32XXAD_CTRL(st->adc_base)); in lpc32xx_read_raw()
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/linux-6.12.1/drivers/clk/nxp/
Dclk-lpc32xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
12 #include <dt-bindings/clock/lpc32xx-clock.h>
284 LPC32XX_CLK_DEFINE(ADC, "adc", 0x0,
393 regmap_read(clk_regmap, clk->reg, &val); in clk_mask_enable()
395 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy) in clk_mask_enable()
396 return -EBUSY; in clk_mask_enable()
398 return regmap_update_bits(clk_regmap, clk->reg, in clk_mask_enable()
399 clk->enable_mask, clk->enable); in clk_mask_enable()
406 regmap_update_bits(clk_regmap, clk->reg, in clk_mask_disable()
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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