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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dqcom,sc8280xp-lpasscc.yaml52 lpass_audiocc: clock-controller@32a9000 {
Dqcom,sc7280-lpasscorecc.yaml134 lpass_audiocc: clock-controller@3300000 {
/linux-6.12.1/Documentation/devicetree/bindings/soundwire/
Dqcom,soundwire.yaml258 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsc7280.dtsi2524 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2578 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>;
2598 lpass_audiocc: clock-controller@3300000 { label
2683 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>,
2684 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>,
2685 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>,
2686 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>,
Dx1e80100.dtsi3546 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
3596 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
3662 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
3684 lpass_audiocc: clock-controller@6b6c000 { label
Dsc8280xp.dtsi2833 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2909 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2933 lpass_audiocc: clock-controller@32a9000 { label