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/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
18 one CPU local timer instantiated in MCT for every CPU in the system.
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Dmarvell,armada-370-xp-timer.txt1 Marvell Armada 370 and Armada XP Timers
2 ---------------------------------------
5 - compatible: Should be one of the following
6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
10 then local timer interrupts
11 - reg: Should contain location and length for timers register. First
13 local/private timers.
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/linux-6.12.1/Documentation/timers/
Dhighres.rst2 High resolution timers and dynamic ticks design notes
8 https://www.kernel.org/doc/ols/2006/ols2006v1-pages-333-346.pdf
11 http://www.cs.columbia.edu/~nahum/w6998/papers/ols2006-hrtimers-slides.pdf
23 - hrtimer base infrastructure
24 - timeofday and clock source management
25 - clock event management
26 - high resolution timer functionality
27 - dynamic ticks
31 ---------------------------
34 the base implementation are covered in Documentation/timers/hrtimers.rst. See
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Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
12 architecture-specific overrides of the sched_clock() function and some
13 delay timers.
17 on this timeline, providing facilities such as high-resolution timers.
18 sched_clock() is used for scheduling and timestamping, and delay timers
23 -------------
31 n bits which count from 0 to (2^n)-1 and then wraps around to 0 and start over.
36 shall be as stable and correct as possible as compared to a real-world wall
46 When the wall-clock accuracy of the clock source isn't satisfactory, there
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/linux-6.12.1/kernel/
Dcpu_pm.c1 // SPDX-License-Identifier: GPL-2.0-only
53 * cpu_pm_register_notifier - register a driver with cpu_pm
74 * cpu_pm_unregister_notifier - unregister a driver with cpu_pm
94 * cpu_pm_enter - CPU low power entry notifier
102 * co-processor, interrupt controller and its PM extensions, local CPU
103 * timers context save/restore which shouldn't be interrupted. Hence it
115 * cpu_pm_exit - CPU low power exit notifier
120 * Notified drivers can include VFP co-processor, interrupt controller
121 * and its PM extensions, local CPU timers context save/restore which
133 * cpu_cluster_pm_enter - CPU cluster low power entry notifier
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/linux-6.12.1/Documentation/virt/hyperv/
Dclocks.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Clocks and Timers
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
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/linux-6.12.1/kernel/time/
Dtimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Kernel internal timers
7 * 1997-01-28 Modified by Finn Arne Gangstad to make timers scale better.
9 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
11 * 1998-12-24 Fixed a xtime SMP race (we need the xtime_lock rw spinlock to
14 * 1999-03-10 Improved NTP compatibility by Ulrich Windl
15 * 2002-05-31 Move sys_sysinfo here and make its locking sane, Robert Love
16 * 2000-10-05 Implemented scalable SMP per-CPU timer handling.
33 #include <linux/posix-timers.h>
55 #include "tick-internal.h"
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Dtimer_migration.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Infrastructure for migratable timers
15 #include "tick-internal.h"
34 * GRP0:0 - GRP0:2 GRP0:3 - GRP0:5
37 * CPUS 0-7 8-15 16-23 24-31 32-39 40-47
45 * active CPUs in a group try to migrate expired timers from other CPUs,
53 * If it finds expired timers in one of the group queues it pulls them over
57 * CPUs which go idle arm their CPU local timer hardware for the next local
59 * next local timer or the CPU has no migratable timer pending then the
61 * timer expires before the next local timer then the CPU queues that timer
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Dhrtimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de>
4 * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar
5 * Copyright(C) 2006-2007 Timesys Corp., Thomas Gleixner
7 * High-resolution kernel timers
9 * In contrast to the low-resolution timeout API, aka timer wheel,
50 #include "tick-internal.h"
53 * Masks for selecting the soft and hard context timers from
54 * cpu_base->active
57 #define HRTIMER_ACTIVE_HARD ((1U << MASK_SHIFT) - 1)
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Dtimer_migration.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * struct tmigr_event - a timer event associated to a CPU
22 * struct tmigr_group - timer migration hierarchy group
47 * group information is NUMA local. It is set to NUMA node
76 * struct tmigr_cpu - timer migration per CPU group
86 * global timers on its own and must not act as a migrator.
89 * @remote: Is set when timers of the CPU are expired remotely
110 * union tmigr_state - state of tmigr_group
111 * @state: Combined version of the state - only used for atomic
113 * @struct: Split version of the state - only use the struct members to
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/linux-6.12.1/net/mac80211/
Dpm.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2020-2021, 2023-2024 Intel Corporation
11 #include "driver-ops.h"
14 static void ieee80211_sched_scan_cancel(struct ieee80211_local *local) in ieee80211_sched_scan_cancel() argument
16 if (ieee80211_request_sched_scan_stop(local)) in ieee80211_sched_scan_cancel()
18 cfg80211_sched_scan_stopped_locked(local->hw.wiphy, 0); in ieee80211_sched_scan_cancel()
23 struct ieee80211_local *local = hw_to_local(hw); in __ieee80211_suspend() local
27 if (!local->open_count) in __ieee80211_suspend()
30 local->suspending = true; in __ieee80211_suspend()
33 ieee80211_scan_cancel(local); in __ieee80211_suspend()
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/linux-6.12.1/drivers/clocksource/
Dbcm_kona_timer.c1 // SPDX-License-Identifier: GPL-2.0
32 static struct kona_bcm_timers timers; variable
37 * We use the peripheral timers for system tick, the cpu global timer for
65 * Read 64-bit free running counter in kona_timer_get_counter()
66 * 1. Read hi-word in kona_timer_get_counter()
67 * 2. Read low-word in kona_timer_get_counter()
68 * 3. Read hi-word again in kona_timer_get_counter()
70 * if new hi-word is not equal to previously read hi-word, then in kona_timer_get_counter()
73 * if new hi-word is equal to previously read hi-word then stop. in kona_timer_get_counter()
81 } while (--loop_limit); in kona_timer_get_counter()
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Dexynos_mct.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7 * Exynos4 MCT(Multi-Core Timer) support
63 /* There are four Global timers starting with 0 offset */
65 /* Local timers count starts after global timer count */
69 /* Max number of local timers */
70 #define MCT_NR_LOCAL (MCT_NR_IRQS - MCT_L0_IRQ)
87 * local timer interrupts grow over two digits
167 * exynos4_read_count_64 - Read all 64-bits of the global counter
169 * This will read all 64-bits of the global counter taking care to make sure
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Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <linux/arm-smccc.h>
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
109 * 2) a roll-over time of not less than 40 years
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64); in arch_counter_get_width()
133 writel_relaxed((u32)val, timer->base + CNTP_CTL); in arch_timer_reg_write()
140 writeq_relaxed(val, timer->base + CNTP_CVAL_LO); in arch_timer_reg_write()
149 writel_relaxed((u32)val, timer->base + CNTV_CTL); in arch_timer_reg_write()
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Darc_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1, Each can be
11 * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
26 #include <soc/arc/timers.h>
65 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's in arc_read_gfrc()
70 * trying to access two different sub-components (like GFRC, in arc_read_gfrc()
71 * inter-core interrupt, etc...). HW also supports simultaneously in arc_read_gfrc()
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Dtimer-fttmr010.c1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
46 * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
62 * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
63 * The aspeed timers move bits around in the control register and lacks
78 * timers.
79 * The registers don't exist and they are not needed on aspeed timers
81 * - aspeed timer overflow interrupt is controlled by bits in Control
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
23 "#interrupt-cells":
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/linux-6.12.1/include/linux/usb/
Dotg-fsm.h1 // SPDX-License-Identifier: GPL-2.0+
18 * Table:6-4
23 * Table:6-5
29 /* Standard OTG timers */
38 /* Auxiliary timers */
49 * struct otg_fsm - OTG state machine according to the OTG spec
54 * @id: TRUE for B-device, FALSE for A-device.
56 * ADP measurement taken at n-2, differs by more than CADP_THR
60 * A-Device state inputs
61 * @a_srp_det: TRUE if the A-device detects SRP
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/linux-6.12.1/Documentation/virt/kvm/x86/
Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
55 available, but not all modes are available to all timers, as only timer 2
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
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/linux-6.12.1/arch/x86/kernel/
Di8253.c1 // SPDX-License-Identifier: GPL-2.0
19 * the two timers is used
29 * requires to know the local APIC timer frequency as it normally is
63 * - On SMP PIT does not scale due to i8253_lock in init_pit_clocksource()
64 * - when HPET is enabled in init_pit_clocksource()
65 * - when local APIC timer is active (PIT is switched off) in init_pit_clocksource()
/linux-6.12.1/net/llc/
Dllc_conn.c2 * llc_conn.c - Driver routines for connection component.
5 * 2001-2003 by Arnaldo Carvalho de Melo <acme@conectiva.com.br>
51 * llc_conn_state_process - sends event to connection state machine
65 struct llc_sock *llc = llc_sk(skb->sk); in llc_conn_state_process()
68 ev->ind_prim = ev->cfm_prim = 0; in llc_conn_state_process()
72 rc = llc_conn_service(skb->sk, skb); in llc_conn_state_process()
78 switch (ev->ind_prim) { in llc_conn_state_process()
94 * skb->sk pointing to the newly created struct sock in in llc_conn_state_process()
95 * llc_conn_handler. -acme in llc_conn_state_process()
98 skb_queue_tail(&sk->sk_receive_queue, skb); in llc_conn_state_process()
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/linux-6.12.1/include/net/sctp/
Dcommand.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1999-2001 Cisco, Motorola
12 * lksctp developers <linux-sctp@vger.kernel.org>
55 SCTP_CMD_COOKIEECHO_RESTART, /* High level, do cookie-echo timer work. */
59 SCTP_CMD_HB_TIMERS_START, /* Start the heartbeat timers. */
60 SCTP_CMD_HB_TIMER_UPDATE, /* Update a heartbeat timers. */
61 SCTP_CMD_HB_TIMERS_STOP, /* Stop the heartbeat timers. */
73 SCTP_CMD_SETUP_T2, /* Hi-level, setup T2-shutdown parms. */
82 SCTP_CMD_DEL_NON_PRIMARY, /* Removes non-primary peer transports. */
83 SCTP_CMD_T3_RTX_TIMERS_STOP, /* Stops T3-rtx pending timers */
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/linux-6.12.1/drivers/net/wireless/ath/ath5k/
Dpcu.c2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
40 * - Buffering of RX and TX frames (after QCU/DCUs)
42 * - Encrypting and decrypting (using the built-in engine)
44 * - Generating ACKs, RTS/CTS frames
46 * - Maintaining TSF
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/linux-6.12.1/Documentation/process/
Dmaintainer-tip.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------------
11 aggregation tree for several sub-maintainer trees. The tip tree gitweb URL
16 - **x86 architecture**
22 x86-specific KVM and XEN patches.
30 mail alias which distributes mails to the x86 top-level maintainer
32 ``linux-kernel@vger.kernel.org``, otherwise your mail ends up only in
35 - **Scheduler**
37 Scheduler development takes place in the -tip tree, in the
38 sched/core branch - with occasional sub-topic trees for
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/linux-6.12.1/arch/mips/cavium-octeon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 non-CN63XXP1 hardware, so it is recommended to select "n"
21 local memory; the larger CVMSEG is, the smaller the cache is.
87 the CIU Timers on Octeon.
90 will be called octeon-ilm

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