| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | rockchip,rk3588-hdptx-phy.yaml | 44 - description: LCPLL reset line
54 - const: lcpll
91 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | brcm,iproc-clocks.yaml | 38 - brcm,ns2-lcpll-ddr
39 - brcm,ns2-lcpll-ports
49 - brcm,sr-lcpll-pcie
203 - brcm,ns2-lcpll-ddr
204 - brcm,ns2-lcpll-ports
262 - brcm,sr-lcpll-pcie
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| D | microchip,sparx5-dpll.yaml | 40 lcpll_clk: lcpll-clk {
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| /linux-6.12.1/include/dt-bindings/clock/ |
| D | bcm-ns2.h | 54 /* LCPLL DDR clock channel ID */
63 /* LCPLL PORTS clock channel ID */
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| D | bcm-sr.h | 95 /* LCPLL PCIE clock channel ID */
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| /linux-6.12.1/arch/arm64/boot/dts/broadcom/northstar2/ |
| D | ns2-clock.dtsi | 43 compatible = "brcm,ns2-lcpll-ddr";
56 compatible = "brcm,ns2-lcpll-ports";
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 81 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
85 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
89 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
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| D | intel_display_power.c | 1162 * The LCPLL register should be turned on by the BIOS. For now in hsw_assert_cdclk()
1168 drm_err(&dev_priv->drm, "CDCLK source is not LCPLL\n"); in hsw_assert_cdclk()
1171 drm_err(&dev_priv->drm, "LCPLL is disabled\n"); in hsw_assert_cdclk()
1174 drm_err(&dev_priv->drm, "LCPLL not using non-SSC reference\n"); in hsw_assert_cdclk()
1220 * gen-specific and since we only disable LCPLL after we fully disable in assert_can_disable_lcpll()
1249 * - Sequence for display software to disable LCPLL
1251 * The steps implemented here are just the steps that actually touch the LCPLL
1280 drm_err(&dev_priv->drm, "LCPLL still locked\n"); in hsw_disable_lcpll()
1298 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
1333 drm_err(&dev_priv->drm, "LCPLL not locked yet\n"); in hsw_restore_lcpll()
[all …]
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| D | intel_cdclk.c | 508 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in hsw_get_cdclk() local
509 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; in hsw_get_cdclk()
511 if (lcpll & LCPLL_CD_SOURCE_FCLK) in hsw_get_cdclk()
792 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL); in bdw_get_cdclk() local
793 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK; in bdw_get_cdclk()
795 if (lcpll & LCPLL_CD_SOURCE_FCLK) in bdw_get_cdclk()
875 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
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| D | intel_dpll_mgr.c | 1310 { .name = "LCPLL 810", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_810,
1312 { .name = "LCPLL 1350", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_1350,
1314 { .name = "LCPLL 2700", .funcs = &hsw_ddi_lcpll_funcs, .id = DPLL_ID_LCPLL_2700,
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| D | intel_backlight.c | 344 * driver. Disable to avoid warnings on LCPLL disable. in lpt_disable_backlight()
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| /linux-6.12.1/drivers/clk/bcm/ |
| D | clk-ns2.c | 215 CLK_OF_DECLARE(ns2_lcpll_ddr_clk, "brcm,ns2-lcpll-ddr",
277 CLK_OF_DECLARE(ns2_lcpll_ports_clk, "brcm,ns2-lcpll-ports",
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| D | clk-sr.c | 399 { .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
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| /linux-6.12.1/drivers/net/phy/mscc/ |
| D | mscc_serdes.c | 288 /* Access LCPLL Cfg_0 */
327 /* Detune/Unlock LCPLL */ in vsc85xx_sd6g_config_v2()
521 /* Tune/Re-lock LCPLL */ in vsc85xx_sd6g_config_v2()
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| D | mscc_main.c | 1256 /* Access LCPLL Cfg_2 */
1301 /* Sequence to Reset LCPLL for the VIPER and ELISE PHY */
1312 /* Reset LCPLL */ in vsc8584_pll5g_reset()
1315 /* write back LCPLL MCB */ in vsc8584_pll5g_reset()
1320 /* 10 mSec sleep while LCPLL is hold in reset */ in vsc8584_pll5g_reset()
1323 /* read LCPLL MCB into CSRs */ in vsc8584_pll5g_reset()
1329 /* Release the Reset of LCPLL */ in vsc8584_pll5g_reset()
1332 /* write back LCPLL MCB */ in vsc8584_pll5g_reset()
1382 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); in vsc8584_config_pre_init()
1999 dev_err(dev, "failed LCPLL reset, ret: %d\n", ret); in vsc8514_config_pre_init()
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| /linux-6.12.1/arch/arm64/boot/dts/microchip/ |
| D | sparx5.dtsi | 79 lcpll_clk: lcpll-clk {
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| /linux-6.12.1/drivers/phy/rockchip/ |
| D | phy-rockchip-usbdp.c | 740 /* LCPLL check */ in rk_udphy_status_check()
746 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); in rk_udphy_status_check()
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| D | phy-rockchip-samsung-hdptx.c | 1107 hdptx->rsts[RST_LCPLL].id = "lcpll"; in rk_hdptx_phy_probe()
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| /linux-6.12.1/drivers/net/ethernet/microchip/sparx5/ |
| D | sparx5_main.c | 490 /* Configure the LCPLL */ in sparx5_init_coreclock()
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| /linux-6.12.1/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_reg.h | 1740 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1770 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
1773 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
1775 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
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| D | bnx2x_link.c | 8600 /* Put LCPLL in low power mode */ in bnx2x_warpcore_hw_reset()
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| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk3588-base.dtsi | 2779 "lcpll";
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| /linux-6.12.1/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 4035 /* LCPLL Control */
|