Searched full:lane3 (Results 1 – 5 of 5) sorted by relevance
61 lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =63 phy lane1, DP lane2 on Type-C phy lane2, DP lane3 on Type-C phy lane3. If
245 uint8_t lane3:2; /* Mapping for lane 3 */ member
189 "cp0-pcie0-x4-lane2-phy", "cp0-pcie0-x4-lane3-phy";
216 /* HS RX Control of lane3 */ in rk_dphy_enable()
101 <bitfield name="LANE3" pos="7" type="boolean"/>