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Searched +full:kona +full:- +full:sdhci (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dbrcm,kona-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,kona-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona family SDHCI controller
10 - Florian Fainelli <f.fainelli@gmail.com>
13 - $ref: sdhci-common.yaml#
17 const: brcm,kona-sdhci
29 - compatible
30 - reg
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/linux-6.12.1/arch/arm/boot/dts/broadcom/
Dbcm11351.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012-2013 Broadcom Corporation
4 #include <dt-bindings/clock/bcm281xx.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&gic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
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Dbcm2166x-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 /dts-v1/;
11 #include <dt-bindings/clock/bcm21664.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
20 hub: hub-bus@34000000 {
21 compatible = "simple-bus";
23 #address-cells = <1>;
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Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/linux-6.12.1/drivers/mmc/host/
Dsdhci-bcm-kona.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/mmc/slot-gpio.h>
16 #include "sdhci-pltfm.h"
17 #include "sdhci.h"
63 return -EFAULT; in sdhci_bcm_kona_sd_reset()
72 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_reset()
73 * Back-to-Back writes to same register needs delay when SD bus clock in sdhci_bcm_kona_sd_reset()
74 * is very low w.r.t AHB clock, mainly during boot-time and during card in sdhci_bcm_kona_sd_reset()
75 * insert-removal. in sdhci_bcm_kona_sd_reset()
97 * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS) in sdhci_bcm_kona_sd_init()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
7 armmmci-y := mmci.o
8 armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
9 armmmci-$(CONFIG_MMC_STM32_SDMMC) += mmci_stm32_sdmmc.o
10 obj-$(CONFIG_MMC_PXA) += pxamci.o
11 obj-$(CONFIG_MMC_MXC) += mxcmmc.o
12 obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
13 obj-$(CONFIG_MMC_SDHCI) += sdhci.o
14 obj-$(CONFIG_MMC_SDHCI_PCI) += sdhci-pci.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
85 need to overwrite SDHCI IO memory accessors.
93 and performing I/O to a SDHCI controller through a bus that
94 implements a hardware byte swapper using a 32-bit datum.
99 This is the case for the Nintendo Wii SDHCI.
102 tristate "SDHCI support on PCI bus"
121 proprietary controller is unnecessary because the SDHCI driver
123 disabled, it will steal the MMC cards away - rendering them
130 tristate "SDHCI support for ACPI enumerated SDHCI controllers"
134 This selects support for ACPI enumerated SDHCI controllers,
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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