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/linux-6.12.1/drivers/phy/starfive/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
16 phy-jh7110-dphy-rx.ko.
19 tristate "StarFive JH7110 D-PHY TX Support"
24 Choose this option if you have a StarFive D-PHY TX in your
26 phy-jh7110-dphy-tx.ko.
29 tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
33 Enable this to support the StarFive PCIe 2.0 PHY,
36 phy-jh7110-pcie.ko.
[all …]
Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 PCIe 2.0 PHY driver
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
58 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
62 regmap_update_bits(data->sys_syscon, data->sys_phy_connect, in phy_usb3_mode_set()
65 /* Configuare spread-spectrum mode: down-spread-spectrum */ in phy_usb3_mode_set()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) += phy-jh7110-dphy-rx.o
3 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) += phy-jh7110-dphy-tx.o
4 obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
5 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe 2.0 PHY
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux-6.12.1/Documentation/devicetree/bindings/pci/
Dstarfive,jh7110-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe host controller
10 - Kevin Xie <kevin.xie@starfivetech.com>
13 - $ref: plda,xpressrich3-axi-common.yaml#
17 const: starfive,jh7110-pcie
21 - description: NOC bus clock
22 - description: Transport layer clock
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/linux-6.12.1/drivers/pci/controller/plda/
Dpcie-starfive.c1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for StarFive JH7110 Soc.
27 #include "pcie-plda.h"
67 * JH7110 PCIe port BAR0/1 can be configured as 64-bit prefetchable memory
68 * space. PCIe read and write requests targeting BAR0/1 are routed to so called
71 * JH7110 can access the Bridge Configuration space by local bus, and don`t
105 static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie, in starfive_pcie_parse_dt() argument
110 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks); in starfive_pcie_parse_dt()
111 if (pcie->num_clks < 0) in starfive_pcie_parse_dt()
112 return dev_err_probe(dev, pcie->num_clks, in starfive_pcie_parse_dt()
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/linux-6.12.1/Documentation/devicetree/bindings/soc/starfive/
Dstarfive,jh7110-syscon.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 SoC system controller
10 - William Qiu <william.qiu@starfivetech.com>
13 The StarFive JH7110 SoC system controller provides register information such
14 as offset, mask and shift to configure related modules such as MMC and PCIe.
19 - items:
20 - const: starfive,jh7110-sys-syscon
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/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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/linux-6.12.1/drivers/usb/cdns3/
DKconfig8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
34 Cadence USBSS-DEV driver.
51 tristate "Cadence USB3 support on PCIe-based platforms"
55 If you're using the USBSS Core IP with a PCIe, please say
59 be dynamically linked and module will be called cdns3-pci.ko
88 e.g. JH7110.
[all …]
/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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