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/linux-6.12.1/drivers/irqchip/
Dirq-ti-sci-intr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
24 * @out_irqs: TISCI resource pointer representing INTR irqs.
26 * @ti_sci_id: TI-SCI device identifier
27 * @type: Specifies the trigger type supported by this Interrupt Router
34 u32 type; member
38 .name = "INTR",
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
53 * @type: IRQ type
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/idpf/
Didpf_vf_dev.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * idpf_vf_ctlq_reg_init - initialize default mailbox registers
21 switch (ccq->type) { in idpf_vf_ctlq_reg_init()
24 ccq->reg.head = VF_ATQH; in idpf_vf_ctlq_reg_init()
25 ccq->reg.tail = VF_ATQT; in idpf_vf_ctlq_reg_init()
26 ccq->reg.len = VF_ATQLEN; in idpf_vf_ctlq_reg_init()
27 ccq->reg.bah = VF_ATQBAH; in idpf_vf_ctlq_reg_init()
28 ccq->reg.bal = VF_ATQBAL; in idpf_vf_ctlq_reg_init()
29 ccq->reg.len_mask = VF_ATQLEN_ATQLEN_M; in idpf_vf_ctlq_reg_init()
30 ccq->reg.len_ena_mask = VF_ATQLEN_ATQENABLE_M; in idpf_vf_ctlq_reg_init()
[all …]
Didpf_dev.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * idpf_ctlq_reg_init - initialize default mailbox registers
21 switch (ccq->type) { in idpf_ctlq_reg_init()
24 ccq->reg.head = PF_FW_ATQH; in idpf_ctlq_reg_init()
25 ccq->reg.tail = PF_FW_ATQT; in idpf_ctlq_reg_init()
26 ccq->reg.len = PF_FW_ATQLEN; in idpf_ctlq_reg_init()
27 ccq->reg.bah = PF_FW_ATQBAH; in idpf_ctlq_reg_init()
28 ccq->reg.bal = PF_FW_ATQBAL; in idpf_ctlq_reg_init()
29 ccq->reg.len_mask = PF_FW_ATQLEN_ATQLEN_M; in idpf_ctlq_reg_init()
30 ccq->reg.len_ena_mask = PF_FW_ATQLEN_ATQENABLE_M; in idpf_ctlq_reg_init()
[all …]
/linux-6.12.1/drivers/net/ethernet/pensando/ionic/
Dionic_dev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
17 struct ionic_lif *lif = ionic->lif; in ionic_watchdog_cb()
21 mod_timer(&ionic->watchdog_timer, in ionic_watchdog_cb()
22 round_jiffies(jiffies + ionic->watchdog_period)); in ionic_watchdog_cb()
28 dev_dbg(ionic->dev, "%s: hb %d running %d UP %d\n", in ionic_watchdog_cb()
29 __func__, hb, netif_running(lif->netdev), in ionic_watchdog_cb()
30 test_bit(IONIC_LIF_F_UP, lif->state)); in ionic_watchdog_cb()
33 !test_bit(IONIC_LIF_F_FW_RESET, lif->state)) in ionic_watchdog_cb()
36 if (test_bit(IONIC_LIF_F_FILTER_SYNC_NEEDED, lif->state) && in ionic_watchdog_cb()
[all …]
/linux-6.12.1/drivers/tty/serial/jsm/
Djsm_neo.c1 // SPDX-License-Identifier: GPL-2.0+
25 * a non-destructive, read-only location on the Neo card.
27 * In this case, we are reading the DVID (Read-only Device Identification)
32 readb(bd->re_map_membase + 0x8D); in neo_pci_posting_flush()
38 ier = readb(&ch->ch_neo_uart->ier); in neo_set_cts_flow_control()
39 efr = readb(&ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
41 jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n"); in neo_set_cts_flow_control()
51 writeb(0, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
54 writeb(efr, &ch->ch_neo_uart->efr); in neo_set_cts_flow_control()
57 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr); in neo_set_cts_flow_control()
[all …]
/linux-6.12.1/drivers/parisc/
Diosapic_private.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
28 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
35 ** Interrupt Type of 0 indicates a vectored interrupt,
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/
Dfalcon.c32 struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); in nvkm_falcon_oclass_get()
35 while (falcon->func->sclass[c].oclass) { in nvkm_falcon_oclass_get()
37 oclass->base = falcon->func->sclass[index]; in nvkm_falcon_oclass_get()
49 return nvkm_gpuobj_new(object->engine->subdev.device, 256, in nvkm_falcon_cclass_bind()
62 struct nvkm_subdev *subdev = &falcon->engine.subdev; in nvkm_falcon_intr()
63 struct nvkm_device *device = subdev->device; in nvkm_falcon_intr()
64 const u32 base = falcon->addr; in nvkm_falcon_intr()
66 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); in nvkm_falcon_intr() local
73 if (intr & 0x00000040) { in nvkm_falcon_intr()
74 if (falcon->func->intr) { in nvkm_falcon_intr()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
25 compatible = "ti,am654-timer";
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 ti,timer-pwm;
[all …]
Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
[all …]
Dk3-am62a-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
19 compatible = "ti,j721e-esm";
21 bootph-pre-ram;
23 ti,esm-pins = <0>, <1>, <2>, <85>;
32 compatible = "ti,am654-timer";
[all …]
Dk3-am62p-j722s-common-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "pinctrl-single";
12 #pinctrl-cells = <1>;
13 pinctrl-single,register-width = <32>;
14 pinctrl-single,function-mask = <0xffffffff>;
15 pinctrl-single,gpio-range =
19 bootph-all;
21 mcu_pmx_range: gpio-range {
22 #pinctrl-single,gpio-range-cells = <3>;
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
Dbase.c29 struct nvkm_subdev *subdev = &wait->tmr->subdev; in nvkm_timer_wait_test()
30 u64 time = nvkm_timer_read(wait->tmr); in nvkm_timer_wait_test()
32 if (wait->reads == 0) { in nvkm_timer_wait_test()
33 wait->time0 = time; in nvkm_timer_wait_test()
34 wait->time1 = time; in nvkm_timer_wait_test()
37 if (wait->time1 == time) { in nvkm_timer_wait_test()
38 if (wait->reads++ == 16) { in nvkm_timer_wait_test()
40 return -ETIMEDOUT; in nvkm_timer_wait_test()
43 wait->time1 = time; in nvkm_timer_wait_test()
44 wait->reads = 1; in nvkm_timer_wait_test()
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dgf100.c43 nvkm_wr32(chan->cgrp->runl->fifo->engine.subdev.device, 0x002634, chan->id); in gf100_chan_preempt()
49 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gf100_chan_stop()
51 nvkm_mask(device, 0x003004 + (chan->id * 8), 0x00000001, 0x00000000); in gf100_chan_stop()
57 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gf100_chan_start()
59 nvkm_wr32(device, 0x003004 + (chan->id * 8), 0x001f0001); in gf100_chan_start()
67 struct nvkm_fifo *fifo = chan->cgrp->runl->fifo; in gf100_chan_unbind()
68 struct nvkm_device *device = fifo->engine.subdev.device; in gf100_chan_unbind()
70 /*TODO: Is this cargo-culted, or necessary? RM does *something* here... Why? */ in gf100_chan_unbind()
73 nvkm_wr32(device, 0x003000 + (chan->id * 8), 0x00000000); in gf100_chan_unbind()
79 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in gf100_chan_bind()
[all …]
/linux-6.12.1/drivers/net/ethernet/intel/igc/
Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
190 /* NVM Addressing bits based on type 0=small, 1=large */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
262 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
269 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
284 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
[all …]
/linux-6.12.1/drivers/iio/accel/
Dbmc150-accel-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * 3-axis accelerometer driver supporting many Bosch-Sensortec chips
20 #include <linux/iio/trigger.h>
26 #include "bmc150-accel.h"
212 struct device *dev = regmap_get_device(data->regmap); in bmc150_accel_set_mode()
216 int dur_val = -1; in bmc150_accel_set_mode()
231 return -EINVAL; in bmc150_accel_set_mode()
238 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); in bmc150_accel_set_mode()
256 ret = regmap_write(data->regmap, in bmc150_accel_set_bw()
262 data->bw_bits = in bmc150_accel_set_bw()
[all …]
/linux-6.12.1/arch/mips/kvm/
Dmips.c115 return !!(vcpu->arch.pending_exceptions); in kvm_arch_vcpu_runnable()
130 return kvm_mips_callbacks->enable_virtualization_cpu(); in kvm_arch_enable_virtualization_cpu()
135 kvm_mips_callbacks->disable_virtualization_cpu(); in kvm_arch_disable_virtualization_cpu()
138 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type) in kvm_arch_init_vm() argument
140 switch (type) { in kvm_arch_init_vm()
146 /* Unsupported KVM type */ in kvm_arch_init_vm()
147 return -EINVAL; in kvm_arch_init_vm()
150 /* Allocate page table to map GPA -> RPA */ in kvm_arch_init_vm()
151 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc(); in kvm_arch_init_vm()
152 if (!kvm->arch.gpa_mm.pgd) in kvm_arch_init_vm()
[all …]
/linux-6.12.1/drivers/gpu/drm/xe/
Dxe_bo.h1 /* SPDX-License-Identifier: MIT */
24 /* -- */
27 XE_BO_FLAG_VRAM0 << (tile)->id : \
42 /* this one is trigger internally only */
48 #define XE_PTE_MASK (XE_PAGE_SIZE - 1)
49 #define XE_PDE_SHIFT (XE_PTE_SHIFT - 3)
51 #define XE_PDE_MASK (XE_PDES - 1)
55 #define XE_64K_PTE_MASK (XE_64K_PAGE_SIZE - 1)
62 #define XE_PL_STOLEN (TTM_NUM_MEM_TYPES - 1)
64 #define XE_BO_PROPS_INVALID (-1)
[all …]
/linux-6.12.1/arch/powerpc/include/uapi/asm/
Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
9 * since we can keep non-volatile in the thread_struct
11 * by intr code.
56 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
129 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
132 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
138 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
140 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
146 * The transfer totals 34 quadword. Quadwords 0-31 contain the
153 * structures. This also simplifies the implementation of a bi-arch
[all …]
/linux-6.12.1/drivers/scsi/bfa/
Dbfa_core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
43 bfa_isr_unhandled, /* --------- */
44 bfa_isr_unhandled, /* --------- */
45 bfa_isr_unhandled, /* --------- */
46 bfa_isr_unhandled, /* --------- */
47 bfa_isr_unhandled, /* --------- */
48 bfa_isr_unhandled, /* --------- */
[all …]
/linux-6.12.1/arch/x86/kvm/
Dx86.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical
101 val -= modifier; in __shrink_ple_window()
115 kvm_x86_ops.nested_ops->leave_nested(vcpu); in kvm_leave_nested()
120 return vcpu->arch.last_vmentry_cpu != -1; in kvm_vcpu_has_run()
125 return vcpu->arch.exception.pending || in kvm_is_exception_pending()
126 vcpu->arch.exception_vmexit.pending || in kvm_is_exception_pending()
132 vcpu->arch.exception.pending = false; in kvm_clear_exception_queue()
133 vcpu->arch.exception.injected = false; in kvm_clear_exception_queue()
134 vcpu->arch.exception_vmexit.pending = false; in kvm_clear_exception_queue()
[all …]
/linux-6.12.1/arch/x86/kernel/apic/
Dio_apic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/amdkfd/
Dkfd_svm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2020-2021 Advanced Micro Devices, Inc.
84 * svm_range_unlink - unlink svm_range from lists and interval tree
90 * Context: The caller must hold svms->lock
94 pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, in svm_range_unlink()
95 prange, prange->start, prange->last); in svm_range_unlink()
97 if (prange->svm_bo) { in svm_range_unlink()
98 spin_lock(&prange->svm_bo->list_lock); in svm_range_unlink()
99 list_del(&prange->svm_bo_list); in svm_range_unlink()
100 spin_unlock(&prange->svm_bo->list_lock); in svm_range_unlink()
[all …]
/linux-6.12.1/drivers/tty/
Dmoxa.c1 // SPDX-License-Identifier: GPL-2.0+
4 * moxa.c -- MOXA Intellio family multiport serial driver.
6 * Copyright (C) 1999-2000 Moxa Technologies (support@moxa.com).
161 * Dual-Ported RAM
180 #define IntrIntr 0x20 /* received INTR code */
184 #define IntrRxTrigger 0x100 /* rx data count reach trigger value */
185 #define IntrTxTrigger 0x200 /* tx data count below trigger value */
214 /* | | +--- RTS flow */
215 /* | +------ TX Xon/Xoff */
216 /* +--------- RX Xon/Xoff */
[all …]

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