Searched +full:interrupt +full:- +full:map (Results 1 – 25 of 1063) sorted by relevance
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/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
D | fsl,ls-extirq.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Freescale Layerscape External Interrupt Controller 10 - Shawn Guo <shawnguo@kernel.org> 14 LX216xA) support inverting the polarity of certain external interrupt 20 - enum: 21 - fsl,ls1021a-extirq 22 - fsl,ls1043a-extirq [all …]
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D | renesas,rza1-irqc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rza1-irqc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Renesas RZ/A1 Interrupt Controller 10 - Chris Brandt <chris.brandt@renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 14 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas RZ/A1 and 16 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI interrupts, 17 - NMI edge select. [all …]
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/linux-6.12.1/arch/mips/boot/dts/loongson/ |
D | ls7a-pch.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 5 compatible = "simple-bus"; 6 #address-cells = <2>; 7 #size-cells = <2>; 13 pic: interrupt-controller@10000000 { 14 compatible = "loongson,pch-pic-1.0"; 16 interrupt-controller; 17 interrupt-parent = <&htvec>; 18 loongson,pic-base-vec = <0>; 19 #interrupt-cells = <2>; [all …]
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D | loongson64-2k1000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 /dts-v1/; 5 #include <dt-bindings/interrupt-controller/irq.h> 10 #address-cells = <2>; 11 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 21 #clock-cells = <1>; 27 #clock-cells = <0>; 28 compatible = "fixed-clock"; [all …]
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/linux-6.12.1/Documentation/devicetree/bindings/pci/ |
D | mediatek-pcie.txt | 4 - compatible: Should contain one of the following strings: 5 "mediatek,mt2701-pcie" 6 "mediatek,mt2712-pcie" 7 "mediatek,mt7622-pcie" 8 "mediatek,mt7623-pcie" 9 "mediatek,mt7629-pcie" 10 "airoha,en7523-pcie" 11 - device_type: Must be "pci" 12 - reg: Base addresses and lengths of the root ports. 13 - reg-names: Names of the above areas to use during resource lookup. [all …]
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D | xilinx-versal-cpm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 18 - xlnx,versal-cpm-host-1.00 19 - xlnx,versal-cpm5-host 23 - description: CPM system level control and status registers. 24 - description: Configuration space region and bridge registers. [all …]
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D | mvebu-pci.txt | 5 - compatible: one of the following values: 6 marvell,armada-370-pcie 7 marvell,armada-xp-pcie 8 marvell,dove-pcie 9 marvell,kirkwood-pcie 10 - #address-cells, set to <3> 11 - #size-cells, set to <2> 12 - #interrupt-cells, set to <1> 13 - bus-range: PCI bus numbers covered 14 - device_type, set to "pci" [all …]
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D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Sergio Paracuellos <sergio.paracuellos@gmail.com> 14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link 18 .-------. 22 '-------' 27 .------------------. 28 .-----------| HOST/PCI Bridge |------------. [all …]
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D | ralink,rt3883-pci.txt | 7 - compatible: must be "ralink,rt3883-pci" 9 - reg: specifies the physical base address of the controller and 12 - #address-cells: specifies the number of cells needed to encode an 15 - #size-cells: specifies the number of cells used to represent the size 18 - ranges: specifies the translation between child address space and parent 23 - status: indicates the operational status of the device. 28 The main node must have two child nodes which describes the built-in 29 interrupt controller and the PCI host bridge. 31 a) Interrupt controller: 35 - interrupt-controller: identifies the node as an interrupt controller [all …]
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D | xlnx,xdma-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 18 - xlnx,xdma-host-3.00 19 - xlnx,qdma-host-3.00 23 - description: configuration region and XDMA bridge register. 24 - description: QDMA bridge register. [all …]
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D | altr,pcie-root-port.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/altr,pcie-root-port.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Matthew Gerlach <matthew.gerlach@linux.intel.com> 16 - altr,pcie-root-port-1.0 17 - altr,pcie-root-port-2.0 21 - description: TX slave port region 22 - description: Control register access region 23 - description: Hard IP region [all …]
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D | xlnx,nwl-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/xlnx,nwl-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thippeswamy Havalige <thippeswamy.havalige@amd.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml# 18 const: xlnx,nwl-pcie-2.11 22 - description: PCIe bridge registers location. 23 - description: PCIe Controller registers location. [all …]
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D | intel,ixp4xx-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 15 - $ref: /schemas/pci/pci-host-bridge.yaml# 20 - enum: 21 - intel,ixp42x-pci 22 - intel,ixp43x-pci 28 - description: IXP4xx-specific registers [all …]
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D | faraday,ftpci100.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 15 plain and dual PCI. The plain version embeds a cascading interrupt controller 17 chips interrupt controller. 21 The plain variant has 128MiB of non-prefetchable memory space, whereas the 24 Interrupt map considerations: 26 The "dual" variant will get INT A, B, C, D from the system interrupt controller 27 and should point to respective interrupt in that controller in its interrupt-map. [all …]
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D | rockchip,rk3399-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Shawn Lin <shawn.lin@rock-chips.com> 13 - $ref: /schemas/pci/pci-host-bridge.yaml# 14 - $ref: rockchip,rk3399-pcie-common.yaml# 18 const: rockchip,rk3399-pcie 22 reg-names: 24 - const: axi-base [all …]
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/linux-6.12.1/arch/loongarch/boot/dts/ |
D | loongson-2k2000.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 6 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/clock/loongson,ls2k-clk.h> 12 #address-cells = <2>; 13 #size-cells = <2>; 16 #address-cells = <1>; 17 #size-cells = <0>; 34 ref_100m: clock-ref-100m { 35 compatible = "fixed-clock"; [all …]
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/linux-6.12.1/arch/arm/boot/dts/marvell/ |
D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 13 #include "armada-xp.dtsi" 17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 27 #address-cells = <1>; 28 #size-cells = <0>; 29 enable-method = "marvell,armada-xp-smp"; 33 compatible = "marvell,sheeva-v7"; 36 clock-latency = <1000000>; 41 compatible = "marvell,sheeva-v7"; [all …]
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D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 13 #include "armada-xp.dtsi" 17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 enable-method = "marvell,armada-xp-smp"; 32 compatible = "marvell,sheeva-v7"; 35 clock-latency = <1000000>; 40 compatible = "marvell,sheeva-v7"; [all …]
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D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 13 #include "armada-xp.dtsi" 17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp"; 25 #address-cells = <1>; 26 #size-cells = <0>; 27 enable-method = "marvell,armada-xp-smp"; 31 compatible = "marvell,sheeva-v7"; 34 clock-latency = <1000000>; 39 compatible = "marvell,sheeva-v7"; [all …]
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D | armada-385.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 12 #include "armada-38x.dtsi" 19 #address-cells = <1>; 20 #size-cells = <0>; 21 enable-method = "marvell,armada-380-smp"; 25 compatible = "arm,cortex-a9"; 30 compatible = "arm,cortex-a9"; 37 compatible = "marvell,armada-370-pcie"; [all …]
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/linux-6.12.1/drivers/net/ethernet/intel/ice/ |
D | ice_irq.c | 1 // SPDX-License-Identifier: GPL-2.0 9 * ice_init_irq_tracker - initialize interrupt tracker 18 pf->irq_tracker.num_entries = max_vectors; in ice_init_irq_tracker() 19 pf->irq_tracker.num_static = num_static; in ice_init_irq_tracker() 20 xa_init_flags(&pf->irq_tracker.entries, XA_FLAGS_ALLOC); in ice_init_irq_tracker() 24 * ice_deinit_irq_tracker - free xarray tracker 29 xa_destroy(&pf->irq_tracker.entries); in ice_deinit_irq_tracker() 33 * ice_free_irq_res - free a block of resources 41 entry = xa_erase(&pf->irq_tracker.entries, index); in ice_free_irq_res() 46 * ice_get_irq_res - get an interrupt resource [all …]
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/linux-6.12.1/Documentation/core-api/irq/ |
D | irq-domain.rst | 2 The irq_domain interrupt number mapping library 7 This is simple when there is only one interrupt controller, but in 8 systems with multiple interrupt controllers the kernel must ensure 9 that each one gets assigned non-overlapping allocations of Linux 12 The number of interrupt controllers registered as unique irqchips 15 mechanisms as the IRQ core system by modelling their interrupt 16 handlers as irqchips, i.e. in effect cascading interrupt controllers. 18 Here the interrupt number loose all kind of correspondence to 19 hardware interrupt numbers: whereas in the past, IRQ numbers could 21 interrupt controller (i.e. the component actually fireing the [all …]
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/linux-6.12.1/drivers/of/ |
D | irq.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) 8 * Copyright (C) 1996-2001 Cort Dougan 13 * device tree to actual irq numbers on an interrupt controller 31 * irq_of_parse_and_map - Parse and map an interrupt into linux virq space 32 * @dev: Device node of the device whose interrupt is to be mapped 33 * @index: Index of the interrupt to map 50 * of_irq_find_parent - Given a device node, find its interrupt parent node 53 * Return: A pointer to the interrupt parent node, or NULL if the interrupt 65 if (of_property_read_u32(child, "interrupt-parent", &parent)) { in of_irq_find_parent() [all …]
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/linux-6.12.1/arch/arm/boot/dts/airoha/ |
D | en7523.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 #include <dt-bindings/interrupt-controller/irq.h> 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/clock/en7523-clk.h> 9 interrupt-parent = <&gic>; 10 #address-cells = <1>; 11 #size-cells = <1>; 13 reserved-memory { 14 #address-cells = <1>; [all …]
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/linux-6.12.1/drivers/gpio/ |
D | gpio-pcie-idio-24.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * GPIO driver for the ACCES PCIe-IDIO-24 family 6 * This driver supports the following ACCES devices: PCIe-IDIO-24, 7 * PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12. 22 * PLX PEX8311 PCI LCS_INTCSR Interrupt Control/Status 25 * 0: Enable Interrupt Sources (Bit 0) 26 * 1: Enable Interrupt Sources (Bit 1) 27 * 2: Generate Internal PCI Bus Internal SERR# Interrupt 28 * 3: Mailbox Interrupt Enable 29 * 4: Power Management Interrupt Enable [all …]
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