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/linux-6.12.1/Documentation/devicetree/bindings/counter/
Dinterrupt-counter.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/counter/interrupt-counter.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Interrupt counter
10 - Oleksij Rempel <o.rempel@pengutronix.de>
13 A generic interrupt counter to measure interrupt frequency. It was developed
17 Interrupts or gpios are required. If both are defined, the interrupt will
22 const: interrupt-counter
31 - compatible
[all …]
/linux-6.12.1/drivers/comedi/drivers/
Damplc_dio200.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
9 * COMEDI - Linux Control and Measurement Device Interface
24 * [0] - I/O port base address
25 * [1] - IRQ (optional, but commands won't work without it)
32 * ------------- ------------- -------------
34 * 0 PPI-X PPI-X PPI-X
35 * 1 CTR-Y1 PPI-Y PPI-Y
36 * 2 CTR-Y2 CTR-Z1* CTR-Z1
37 * 3 CTR-Z1 INTERRUPT* CTR-Z2
[all …]
Damplc_dio200_pci.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2005-2013 MEV Ltd. <https://www.mev.co.uk/>
8 * COMEDI - Linux Control and Measurement Device Interface
30 * ------------- ------------- -------------
32 * 0 PPI-X PPI-X PPI-X
33 * 1 PPI-Y UNUSED UNUSED
34 * 2 CTR-Z1 PPI-Y UNUSED
35 * 3 CTR-Z2 UNUSED UNUSED
36 * 4 INTERRUPT CTR-Z1 CTR-Z1
37 * 5 CTR-Z2 CTR-Z2
[all …]
Ddas16m1.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Comedi driver for CIO-DAS16/M1
7 * COMEDI - Linux Control and Measurement Device Interface
13 * Description: CIO-DAS16/M1
15 * Devices: [Measurement Computing] CIO-DAS16/M1 (das16m1)
18 * This driver supports a single board - the CIO-DAS16/M1. As far as I know,
20 * CIO-DAS16/M1/16 is significantly different.
23 * a hard real-time interrupt (set the TRIG_RT flag in your struct comedi_cmd
25 * pulling the data across the ISA bus. I timed the interrupt handler, and it
28 * time in the interrupt handler.
[all …]
Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
51 * counter channel.
73 /* Interrupt enable bit in ISR and IER. */
79 #define S626_IRQ_COINT1A 0x0400 /* counter 1A overflow interrupt mask */
80 #define S626_IRQ_COINT1B 0x0800 /* counter 1B overflow interrupt mask */
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/linux-6.12.1/drivers/counter/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Counter devices
8 select COUNTER
21 menuconfig COUNTER config
22 tristate "Counter support"
24 This enables counter device support through the Generic Counter
26 one or more of the counter device drivers below.
28 if COUNTER
31 tristate "ACCES 104-QUAD-8 driver"
37 Say yes here to build support for the ACCES 104-QUAD-8 quadrature
[all …]
Dinterrupt-cnt.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/counter.h>
8 #include <linux/interrupt.h>
15 #define INTERRUPT_CNT_NAME "interrupt-cnt"
29 struct counter_device *counter = dev_id; in interrupt_cnt_isr() local
30 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_isr()
32 atomic_inc(&priv->count); in interrupt_cnt_isr()
34 counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); in interrupt_cnt_isr()
39 static int interrupt_cnt_enable_read(struct counter_device *counter, in interrupt_cnt_enable_read() argument
42 struct interrupt_cnt_priv *priv = counter_priv(counter); in interrupt_cnt_enable_read()
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/linux-6.12.1/drivers/net/wan/
Dhd64572.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * hd64572.h Description of the Hitachi HD64572 (SCA-II), valid for
8 * Copyright: (c) 2000-2001 Cyclades Corp.
15 * PC300 initial CVS version (3.4.0-pre1)
36 /* Interrupt Registers */
37 #define IVR 0x60 /* Interrupt Vector Register */
38 #define IMVR 0x64 /* Interrupt Modified Vector Register */
39 #define ITCR 0x68 /* Interrupt Control Register */
40 #define ISR0 0x6c /* Interrupt Status Register 0 */
41 #define ISR1 0x70 /* Interrupt Status Register 1 */
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/linux-6.12.1/drivers/perf/
Darm_v6_pmu.c1 // SPDX-License-Identifier: GPL-2.0
3 * ARMv6 Performance counter handling code.
7 * ARMv6 has 2 configurable performance counters and a single cycle counter.
16 * the event bus. The procedure for disabling a configurable counter is:
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
18 * effectively stops the counter from counting.
19 * - disable the counter's interrupt generation (each counter has it's
20 * own interrupt enable bit).
21 * Once stopped, the counter value can be written as 0 to reset.
23 * To enable a counter:
[all …]
Dfsl_imx9_ddr_perf.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/interrupt.h>
42 * 32bit counters monitor counter-specific events in addition to counting reference events
94 return pmu->devtype_data == &imx93_devtype_data; in is_imx93()
99 return pmu->devtype_data == &imx95_devtype_data; in is_imx95()
103 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data },
104 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data },
115 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); in ddr_perf_identifier_show()
135 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); in ddr_perf_cpumask_show()
162 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); in ddr_pmu_event_show()
[all …]
/linux-6.12.1/arch/mips/kernel/
Dcevt-r4k.c7 * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/interrupt.h>
17 #include <asm/cevt-r4k.h>
28 res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0; in mips_next_event()
33 * calculate_min_delta() - Calculate a good minimum delta for mips_next_event().
67 cnt = read_c0_count() - cnt; in calculate_min_delta()
73 j, ARRAY_SIZE(buf1) - 1); in calculate_min_delta()
74 for (; l > k; --l) in calculate_min_delta()
75 buf1[l] = buf1[l - 1]; in calculate_min_delta()
85 if (buf1[ARRAY_SIZE(buf1) - 1] < buf2[k]) { in calculate_min_delta()
[all …]
/linux-6.12.1/drivers/net/ethernet/sun/
Dsunbmac.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
44 #define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
45 #define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
46 #define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
47 #define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
52 #define CREG_CCNT 0x30UL /* Collision Counter */
58 #define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
63 #define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
87 /* 0x004-->0x0fc, reserved */
[all …]
/linux-6.12.1/drivers/net/ethernet/freescale/
Dgianfar.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
16 * -Add support for module parameters
17 * -Add patch for ethtool phys id
27 #include <linux/interrupt.h>
67 #define DRV_NAME "gfar-enet"
92 #define GFAR_RXB_SIZE rounddown(GFAR_RXB_TRUESIZE - GFAR_SKBFRAG_OVR, 64)
95 #define TX_RING_MOD_MASK(size) (size-1)
96 #define RX_RING_MOD_MASK(size) (size-1)
108 * time described by a value of 1 in the interrupt
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/linux-6.12.1/drivers/net/ethernet/aquantia/atlantic/hw_atl/
Dhw_atl_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
59 /* get rx dma good octet counter */
62 /* get rx dma good packet counter */
65 /* get tx dma good octet counter */
68 /* get tx dma good packet counter */
71 /* get msm rx errors counter register */
74 /* get msm rx unicast frames counter register */
77 /* get msm rx multicast frames counter register */
[all …]
/linux-6.12.1/drivers/rtc/
Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
17 * DIER (DryIce Interrupt Enable Register) are the only exception. These
36 #define DTCMR 0x00 /* Time Counter MSB Reg */
37 #define DTCLR 0x04 /* Time Counter LSB Reg */
41 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
44 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
45 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
[all …]
/linux-6.12.1/include/linux/mfd/
Dmotorola-cpcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
29 #define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
31 #define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
32 #define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
33 #define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
34 #define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
35 #define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
36 #define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dsamsung,exynos4210-mct.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 global timer and CPU local timers. The global timer is a 64-bit free running
15 up-counter and can generate 4 interrupts when the counter reaches one of the
16 four preset counter values. The CPU local timers are 32-bit free running
17 down-counters and generate an interrupt when the counter expires. There is
23 - enum:
[all …]
/linux-6.12.1/arch/mips/include/asm/sgi/
Dioc.h20 * All registers are 8-bit wide aligned on 32-bit boundary. Bad things
44 volatile u8 istat0; /* Interrupt status zero */
54 volatile u8 imask0; /* Interrupt mask zero */
56 volatile u8 istat1; /* Interrupt status one */
66 volatile u8 imask1; /* Interrupt mask one */
68 volatile u8 vmeistat; /* VME interrupt status */
70 volatile u8 cmeimask0; /* VME interrupt mask zero */
72 volatile u8 cmeimask1; /* VME interrupt mask one */
81 volatile u8 tcnt0; /* counter 0 */
83 volatile u8 tcnt1; /* counter 1 */
[all …]
/linux-6.12.1/drivers/media/pci/cx88/
Dcx88-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * cx88x-hw.h - CX2388x register offsets
5 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
68 #define MO_PCI_INTMSK 0x200040 // PCI interrupt mask
69 #define MO_PCI_INTSTAT 0x200044 // PCI interrupt status
70 #define MO_PCI_INTMSTAT 0x200048 // PCI interrupt masked status
71 #define MO_VID_INTMSK 0x200050 // Video interrupt mask
72 #define MO_VID_INTSTAT 0x200054 // Video interrupt status
73 #define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status
74 #define MO_VID_INTSSTAT 0x20005C // Video interrupt set status
[all …]
/linux-6.12.1/drivers/gpu/drm/i915/display/
Dintel_vblank.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2022-2023 Intel Corporation
27 * increment frame counter (ctg+)
28 * generate start of vblank interrupt (gen4+)
31 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
32 * | may be shifted forward 1-3 extra lines via TRANSCONF
35 * | | generate vsync interrupt
39 * ----va---> <-----------------vb--------------------> <--------va-------------
40 * | | <----vs-----> |
41 …* -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter …
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/linux-6.12.1/Documentation/virt/kvm/x86/
Dtimekeeping.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
44 One of the first timer devices available is the programmable interrupt timer,
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
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/linux-6.12.1/drivers/net/ethernet/cadence/
Dmacb.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2004-2006 Atmel Corporation
14 #include <linux/interrupt.h>
36 #define MACB_ISR 0x0024 /* Interrupt Status */
37 #define MACB_IER 0x0028 /* Interrupt Enable */
38 #define MACB_IDR 0x002c /* Interrupt Disable */
39 #define MACB_IMR 0x0030 /* Interrupt Mask */
109 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
110 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
111 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
[all …]
/linux-6.12.1/arch/mips/include/asm/sn/sn0/
Dhubpi.h8 * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
30 #define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */
65 #define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A)
68 /* Regular Interrupt register checking. */
73 #define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */
74 #define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */
75 #define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */
76 #define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */
82 #define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */
83 #define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */
[all …]
/linux-6.12.1/arch/mips/loongson2ef/common/cs5536/
Dcs5536_mfgpt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/interrupt.h>
36 /* disable counter */
43 /* enable counter, comparator2 to event mode, 14.318MHz clock */
55 outw(0, MFGPT0_CNT); /* set counter to 0 */ in mfgpt_timer_set_periodic()
113 cd->cpumask = cpumask_of(cpu); in setup_mfgpt0_timer()
115 cd->max_delta_ns = clockevent_delta2ns(0xffff, cd); in setup_mfgpt0_timer()
116 cd->max_delta_ticks = 0xffff; in setup_mfgpt0_timer()
117 cd->min_delta_ns = clockevent_delta2ns(0xf, cd); in setup_mfgpt0_timer()
118 cd->min_delta_ticks = 0xf; in setup_mfgpt0_timer()
[all …]
/linux-6.12.1/drivers/clocksource/
Dasm9260_timer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
8 #include <linux/interrupt.h>
19 #define DRIVER_NAME "asm9260-timer"
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
31 #define HW_IR 0x0000 /* RW. Interrupt */
40 * Timer Counter and the Prescale Counter are synchronously reset on the
[all …]

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