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/linux-6.12.1/Documentation/devicetree/bindings/display/bridge/
Dfsl,ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
14 for configuring the on-SoC DPI-to-LVDS serializer. This describes
20 - fsl,imx6sx-ldb
21 - fsl,imx8mp-ldb
22 - fsl,imx93-ldb
27 clock-names:
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/linux-6.12.1/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
26 '#address-cells':
29 '#size-cells':
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/linux-6.12.1/drivers/gpu/drm/bridge/imx/
DMakefile1 obj-$(CONFIG_DRM_IMX_LDB_HELPER) += imx-ldb-helper.o
2 obj-$(CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE) += imx8mp-hdmi-tx.o
3 obj-$(CONFIG_DRM_IMX8MP_HDMI_PVI) += imx8mp-hdmi-pvi.o
4 obj-$(CONFIG_DRM_IMX8QM_LDB) += imx8qm-ldb.o
5 obj-$(CONFIG_DRM_IMX8QXP_LDB) += imx8qxp-ldb.o
6 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_COMBINER) += imx8qxp-pixel-combiner.o
7 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK) += imx8qxp-pixel-link.o
8 obj-$(CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI) += imx8qxp-pxl2dpi.o
9 obj-$(CONFIG_DRM_IMX93_MIPI_DSI) += imx93-mipi-dsi.o
/linux-6.12.1/drivers/gpu/drm/bridge/
Dfsl-ldb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/media-bus-format.h>
99 return (fsl_ldb->ch0_enabled && fsl_ldb->ch1_enabled); in fsl_ldb_is_dual()
120 return drm_bridge_attach(bridge->encoder, fsl_ldb->panel_bridge, in fsl_ldb_attach()
128 struct drm_atomic_state *state = old_bridge_state->base.state; in fsl_ldb_atomic_enable()
143 switch (bridge_state->output_bus_cfg.format) { in fsl_ldb_atomic_enable()
163 dev_warn(fsl_ldb->dev, in fsl_ldb_atomic_enable()
165 bridge_state->output_bus_cfg.format); in fsl_ldb_atomic_enable()
174 bridge->encoder); in fsl_ldb_atomic_enable()
175 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; in fsl_ldb_atomic_enable()
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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Dimx8mp-phyboard-pollux-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h>
12 #include "imx8mp-phycore-som.dtsi"
15 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
16 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
17 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
20 stdout-path = &uart1;
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