| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8mp-hdmi-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mp-hdmi-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8MP HDMI PHY
10 - Lucas Stach <l.stach@pengutronix.de>
15 - fsl,imx8mp-hdmi-phy
20 "#clock-cells":
26 clock-names:
28 - const: apb
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mp-hdmi-blk-ctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HDMI blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
15 peripherals located in the HDMI domain of the SoC.
20 - const: fsl,imx8mp-hdmi-blk-ctrl
21 - const: syscon
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| /linux-6.12.1/drivers/gpu/drm/bridge/imx/ |
| D | imx8mp-hdmi-tx.c | 1 // SPDX-License-Identifier: GPL-2.0+
25 struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data; in imx8mp_hdmi_mode_valid() local
27 if (mode->clock < 13500) in imx8mp_hdmi_mode_valid()
30 if (mode->clock > 297000) in imx8mp_hdmi_mode_valid()
33 if (clk_round_rate(hdmi->pixclk, mode->clock * 1000) != in imx8mp_hdmi_mode_valid()
34 mode->clock * 1000) in imx8mp_hdmi_mode_valid()
37 /* We don't support double-clocked and Interlaced modes */ in imx8mp_hdmi_mode_valid()
38 if ((mode->flags & DRM_MODE_FLAG_DBLCLK) || in imx8mp_hdmi_mode_valid()
39 (mode->flags & DRM_MODE_FLAG_INTERLACE)) in imx8mp_hdmi_mode_valid()
56 static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) in im8mp_hdmi_phy_setup_hpd() argument
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | imx8mp-dhcom-pdk2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * DHCOM iMX8MP variant:
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK2 PCB number: 516-400 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
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| D | imx8mp-dhcom-pdk3.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * DHCOM iMX8MP variant:
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK3 PCB number: 669-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
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| D | imx8mp.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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| D | imx8mp-debix-model-a.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/usb/pd.h>
13 #include "imx8mp.dtsi"
17 compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
20 stdout-path = &uart2;
23 hdmi-connector {
24 compatible = "hdmi-connector";
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| D | imx8mp-beacon-kit.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mp.dtsi"
11 #include "imx8mp-beacon-som.dtsi"
15 compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
23 stdout-path = &uart2;
26 clk_xtal25: clock-xtal25 {
27 compatible = "fixed-clock";
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| D | imx8mp-evk.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include "imx8mp.dtsi"
13 compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
16 stdout-path = &uart2;
19 backlight_lvds: backlight-lvds {
20 compatible = "pwm-backlight";
22 brightness-levels = <0 100>;
23 num-interpolated-steps = <100>;
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| D | imx8mp-data-modul-edm-sbc.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mp.dtsi"
14 compatible = "dmo,imx8mp-data-modul-edm-sbc", "fsl,imx8mp";
22 stdout-path = &uart3;
32 compatible = "pwm-backlight";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_backlight>;
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| D | imx8mp-tqma8mpql-mba8mp-ras314.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
9 /dts-v1/;
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 #include <dt-bindings/pwm/pwm.h>
15 #include "imx8mp-tqma8mpql.dtsi"
18 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314";
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| D | imx8mp-tqma8mpql-mba8mpxl.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2022 TQ-Systems GmbH
4 * Author: Alexander Stein <alexander.stein@tq-group.com>
7 /dts-v1/;
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/pwm/pwm.h>
13 #include "imx8mp-tqma8mpql.dtsi"
16 model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL";
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| D | imx8mp-dhcom-som.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
6 #include "imx8mp.dtsi"
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
29 regulator-always-on;
30 regulator-boot-on;
31 regulator-min-microvolt = <3300000>;
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| D | imx8mp-verdin.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h>
8 #include "imx8mp.dtsi"
12 stdout-path = &uart3;
24 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4>;
28 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default";
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| /linux-6.12.1/drivers/pmdomain/imx/ |
| D | imx8mp-blk-ctrl.c | 1 // SPDX-License-Identifier: GPL-2.0+
9 #include <linux/clk-provider.h>
19 #include <dt-bindings/power/imx8mp-power.h>
104 regmap_update_bits(clk->regmap, GPR_REG2, in clk_hsio_pll_prepare()
110 /* de-assert PLL reset */ in clk_hsio_pll_prepare()
111 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST, PLL_RST); in clk_hsio_pll_prepare()
114 regmap_update_bits(clk->regmap, GPR_REG3, PLL_CKE, PLL_CKE); in clk_hsio_pll_prepare()
116 return regmap_read_poll_timeout(clk->regmap, GPR_REG1, val, in clk_hsio_pll_prepare()
124 regmap_update_bits(clk->regmap, GPR_REG3, PLL_RST | PLL_CKE, 0); in clk_hsio_pll_unprepare()
131 return regmap_test_bits(clk->regmap, GPR_REG1, PLL_LOCK); in clk_hsio_pll_is_prepared()
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| D | gpcv2.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
20 #include <dt-bindings/power/imx7-power.h>
21 #include <dt-bindings/power/imx8mq-power.h>
22 #include <dt-bindings/power/imx8mm-power.h>
23 #include <dt-bindings/power/imx8mn-power.h>
24 #include <dt-bindings/power/imx8mp-power.h>
322 ret = pm_runtime_get_sync(domain->dev); in imx_pgc_power_up()
324 pm_runtime_put_noidle(domain->dev); in imx_pgc_power_up()
328 if (!IS_ERR(domain->regulator)) { in imx_pgc_power_up()
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| /linux-6.12.1/drivers/phy/freescale/ |
| D | phy-fsl-samsung-hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
415 fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy, in fsl_samsung_hdmi_phy_configure_pixclk() argument
420 switch (cfg->pixclk) { in fsl_samsung_hdmi_phy_configure_pixclk()
445 phy->regs + PHY_REG_21); in fsl_samsung_hdmi_phy_configure_pixclk()
449 fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, in fsl_samsung_hdmi_phy_configure_pll_lock_det() argument
452 u32 pclk = cfg->pixclk; in fsl_samsung_hdmi_phy_configure_pll_lock_det()
457 switch (cfg->pixclk) { in fsl_samsung_hdmi_phy_configure_pll_lock_det()
472 writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
492 phy->regs + PHY_REG_13); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
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