Home
last modified time | relevance | path

Searched +full:imx7ulp +full:- +full:clock (Results 1 – 25 of 55) sorted by relevance

123

/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
Dimx7ulp-com.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include "imx7ulp.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
15 stdout-path = &lpuart4;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_lpuart4>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usbotg1_id>;
[all …]
Dimx7ulp-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 /dts-v1/;
10 #include "imx7ulp.dtsi"
14 compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
17 stdout-path = &lpuart4;
26 compatible = "pwm-backlight";
28 brightness-levels = <0 20 25 30 35 40 100>;
29 default-brightness-level = <6>;
33 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
[all …]
Dimxrt1050.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "../../armv7-m.dtsi"
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/imxrt1050-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <24000000>;
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dimx7ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
10 - A.s. Dong <aisheng.dong@nxp.com>
13 i.MX7ULP Clock functions are under joint control of the System
14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
18 and A7 domain. Except for a few clock sources shared between two
19 domains, such as the System Oscillator clock, the Slow IRC (SIRC),
[all …]
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx8ulp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8ulp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/imx8ulp-power.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8ulp-pinfunc.h"
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
[all …]
Dimx93.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/fsl,imx93-power.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx93-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
Dimx95.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
6 #include <dt-bindings/dma/fsl-edma.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx95-clock.h"
13 #include "imx95-pinfunc.h"
14 #include "imx95-power.h"
17 interrupt-parent = <&gic>;
[all …]
Dimx8qm-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
21 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
24 interrupt-parent = <&gic>;
[all …]
Dimx8dxl-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &enet1_lpcg;
7 /delete-node/ &fec2;
10 conn_enet0_root_clk: clock-conn-enet0-root {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <250000000>;
14 clock-output-names = "conn_enet0_root_clk";
17 clk_dummy: clock-dummy {
18 compatible = "fixed-clock";
[all …]
Dimx8dxl-ss-adma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 /delete-node/ &asrc1;
7 /delete-node/ &asrc1_lpcg;
8 /delete-node/ &adc1;
9 /delete-node/ &adc1_lpcg;
10 /delete-node/ &amix;
11 /delete-node/ &amix_lpcg;
12 /delete-node/ &edma1;
13 /delete-node/ &esai0;
14 /delete-node/ &esai0_lpcg;
[all …]
Dimx8-ss-lvds1.dtsi1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
[all …]
Dimx8-ss-conn.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
[all …]
Dimx8-ss-dma.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/dma/fsl-edma.h>
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 dma_ipg_clk: clock-dma-ipg {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <120000000>;
15 clock-output-names = "dma_ipg_clk";
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/watchdog/
Dfsl-imx7ulp-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: watchdog.yaml#
20 - const: fsl,imx7ulp-wdt
21 - items:
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 are clocked by an asynchronous clock that can remain enabled in low
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
26 - const: fsl,imx7ulp-tpm
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Di2c-imx-lpi2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-imx-lpi2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/i2c/i2c-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-lpi2c
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: /schemas/spi/spi-controller.yaml#
20 - enum:
21 - fsl,imx7ulp-spi
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pwm/
Dimx-tpm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
19 - $ref: pwm.yaml#
22 "#pwm-cells":
27 - fsl,imx7ulp-pwm
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/serial/
Dfsl-lpuart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-lpuart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fugang Duan <fugang.duan@nxp.com>
13 - $ref: rs485.yaml#
14 - $ref: serial.yaml#
19 - enum:
20 - fsl,vf610-lpuart
21 - fsl,ls1021a-lpuart
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/dma/
Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
23 - fsl,imx7ulp-edma
24 - fsl,imx8qm-edma
25 - fsl,imx8ulp-edma
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dfsl,mxs-usbphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,mxs-usbphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx23-usbphy
17 - fsl,imx7ulp-usbphy
18 - fsl,vf610-usbphy
19 - items:
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dgpio-vf610.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-vf610.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stefan Agner <stefan@agner.ch>
23 - const: fsl,imx8ulp-gpio
24 - const: fsl,vf610-gpio
25 - items:
26 - const: fsl,imx7ulp-gpio
27 - const: fsl,vf610-gpio
[all …]
/linux-6.12.1/drivers/clk/imx/
Dclk-imx7ulp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/clock/imx7ulp-clock.h>
11 #include <linux/clk-provider.h>
57 clk_data->num = IMX7ULP_CLK_SCG1_END; in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
104 /* scs/ddr/nic select different clock source requires that clock to be enabled first */ in imx7ulp_clk_scg1_init()
111 …re", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk… in imx7ulp_clk_scg1_init()
113 …IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->… in imx7ulp_clk_scg1_init()
129 imx_check_clk_hws(hws, clk_data->num); in imx7ulp_clk_scg1_init()
133 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
[all …]

123