| /linux-6.12.1/Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/ |
| D | link_dpms.c | 31 * TODO - The reason link owns stream's dpms programming sequence is
83 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
84 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
85 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
89 dp_retrieve_lttpr_cap(dc->links[i]); in link_blank_all_dp_displays()
91 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, in link_blank_all_dp_displays()
95 link_blank_dp_stream(dc->links[i], true); in link_blank_all_dp_displays()
106 for (i = 0; i < dc->link_count; i++) { in link_blank_all_edp_displays()
107 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || in link_blank_all_edp_displays()
108 (!dc->links[i]->edp_sink_present)) in link_blank_all_edp_displays()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| D | link_dp_capability.c | 55 link->ctx->logger
108 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && in is_dp_active_dongle()
109 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); in is_dp_active_dongle()
114 return link->dpcd_caps.is_branch_dev; in is_dp_branch_device()
132 return -1; in translate_dpcd_max_bpc()
186 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
189 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
192 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
195 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
198 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| D | dcn20_link_encoder.c | 2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
49 (enc10->link_regs->index)
177 enable ? "Enabling" : "Disabling", enc->id.enum_id); in enc2_fec_set_enable()
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_cx0_phy.c | 1 // SPDX-License-Identifier: MIT
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
122 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_clear_response_ready_flag()
124 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane), in intel_clear_response_ready_flag()
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| D | intel_ddi.c | 99 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
101 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
127 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
136 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
141 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
150 * HDMI/DVI use cases.
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| D | intel_ddi_buf_trans.c | 1 // SPDX-License-Identifier: MIT
14 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
16 * automatically adapt to HDMI connections as well
399 /* BSpec has 2 recommended values - entries 0 and 8.
419 .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
475 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
593 /* Voltage swing pre-emphasis */
612 /* Voltage swing pre-emphasis */
631 /* HDMI Preset VS Pre-emph */
637 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
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| D | intel_dp.c | 93 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
122 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
134 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
142 return drm_dp_is_uhbr_rate(crtc_state->port_clock); in intel_dp_is_uhbr()
146 * intel_dp_link_symbol_size - get the link symbol size for a given link rate
150 * rate -> channel coding.
158 * intel_dp_link_symbol_clock - convert link rate to link symbol clock
172 return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel); in max_dprx_rate()
174 return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in max_dprx_rate()
180 return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel); in max_dprx_lane_count()
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| /linux-6.12.1/sound/pci/hda/ |
| D | patch_hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
172 /* hdmi interrupt trigger control flag for Nvidia codec */
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| /linux-6.12.1/drivers/gpu/drm/amd/include/ |
| D | atomfirmware.h | 6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
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| D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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| /linux-6.12.1/drivers/soc/tegra/ |
| D | pmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
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| /linux-6.12.1/drivers/gpu/drm/radeon/ |
| D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
707 // =3: HDMI encoder
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dce110/ |
| D | dce110_hwseq.c | 74 * For eDP, after power-up/power/down,
84 hws->ctx
87 ctx->logger
89 struct dc_context *ctx = dc->ctx
92 hws->regs->reg
96 hws->shifts->field_name, hws->masks->field_name
104 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
107 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
110 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
113 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
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| /linux-6.12.1/drivers/clk/tegra/ |
| D | clk-tegra-periph.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
714 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
795 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dmub/inc/ |
| D | dmub_cmd.h | 143 * Physical framebuffer address location, 64-bit.
250 * @knee_threshold: Current x-position of ACE knee (u0.16).
270 * union dmub_addr - DMUB physical/virtual 64-bit address.
519 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
526 uint32_t all; /**< 32-bit access to status bits */
530 * struct dmub_fw_meta_info - metadata associated with fw binary
558 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
572 * dmub_trace_code_t - firmware trace code, 32-bits
577 * struct dmcub_trace_buf_entry - Firmware trace entry
601 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
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| /linux-6.12.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_debugfs.c | 66 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
93 return -EFAULT; in parse_write_buffer_into_params()
107 /* skip non-space*/ in parse_write_buffer_into_params()
156 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
158 * --- to get dp configuration
160 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
163 * current -- for current video mode
164 * verified --- maximum configuration which pass link training
165 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
166 * preferred --- user force settings
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| D | amdgpu_dm.c | 183 switch (link->dpcd_caps.dongle_type) { in get_subconnector_type()
202 struct dc_link *link = aconnector->dc_link; in update_subconnector_property()
203 struct drm_connector *connector = &aconnector->base; in update_subconnector_property()
206 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) in update_subconnector_property()
209 if (aconnector->dc_sink) in update_subconnector_property()
212 drm_object_property_set_value(&connector->base, in update_subconnector_property()
213 connector->dev->mode_config.dp_subconnector_property, in update_subconnector_property()
256 * struct amdgpu_device *adev - [in] desired amdgpu device
257 * int disp_idx - [in] which CRTC to get the counter from
266 if (crtc >= adev->mode_info.num_crtc) in dm_vblank_get_counter()
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| /linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn32/ |
| D | dcn32_hwseq.c | 59 hws->ctx
61 hws->regs->reg
63 dc->ctx->logger
67 hws->shifts->field_name, hws->masks->field_name
77 struct dc *dc = hws->ctx->dc; in dcn32_dsc_pg_control()
79 if (dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
82 if (!dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
168 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
201 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
202 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
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