Searched +full:hb +full:- +full:a9periph +full:- +full:clock (Results 1 – 3 of 3) sorted by relevance
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | calxeda.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/calxeda.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda highbank platform Clock Controller
13 "hb-sregs" node.
16 - Andre Przywara <andre.przywara@arm.com>
19 "#clock-cells":
24 - calxeda,hb-pll-clock
25 - calxeda,hb-a9periph-clock
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| /linux-6.12.1/arch/arm/boot/dts/calxeda/ |
| D | ecx-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
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| /linux-6.12.1/drivers/clk/ |
| D | clk-highbank.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
9 #include <linux/clk-provider.h>
48 reg = readl(hbclk->reg); in clk_pll_prepare()
50 writel(reg, hbclk->reg); in clk_pll_prepare()
52 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
54 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
65 reg = readl(hbclk->reg); in clk_pll_unprepare()
67 writel(reg, hbclk->reg); in clk_pll_unprepare()
75 reg = readl(hbclk->reg); in clk_pll_enable()
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