| /linux-6.12.1/tools/perf/pmu-events/arch/riscv/ |
| D | riscv-sbi-firmware.json | 39 "PublicDescription": "Sent IPI to other HART event",
42 "BriefDescription": "Sent IPI to other HART event"
45 "PublicDescription": "Received IPI from other HART event",
48 "BriefDescription": "Received IPI from other HART event"
51 "PublicDescription": "Sent FENCE.I request to other HART event",
54 "BriefDescription": "Sent FENCE.I request to other HART event"
57 "PublicDescription": "Received FENCE.I request from other HART event",
60 "BriefDescription": "Received FENCE.I request from other HART event"
63 "PublicDescription": "Sent SFENCE.VMA request to other HART event",
66 "BriefDescription": "Sent SFENCE.VMA request to other HART event"
[all …]
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| /linux-6.12.1/arch/riscv/kernel/ |
| D | cpu.c | 27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
30 int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_of_processor_hartid() argument
34 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_of_processor_hartid()
35 if (*hart == ~0UL) { in riscv_of_processor_hartid()
36 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
40 cpu = riscv_hartid_to_cpuid(*hart); in riscv_of_processor_hartid()
50 int __init riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) in riscv_early_of_processor_hartid() argument
59 *hart = (unsigned long)of_get_cpu_hwid(node, 0); in riscv_early_of_processor_hartid()
60 if (*hart == ~0UL) { in riscv_early_of_processor_hartid()
[all …]
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| D | smpboot.c | 73 unsigned long hart; in acpi_parse_rintc() local
90 hart = processor->hart_id; in acpi_parse_rintc()
91 if (hart == INVALID_HARTID) { in acpi_parse_rintc()
96 if (hart == cpuid_to_hartid_map(0)) { in acpi_parse_rintc()
107 cpuid_to_hartid_map(cpu_count) = hart; in acpi_parse_rintc()
124 unsigned long hart; in of_parse_and_init_cpus() local
130 rc = riscv_early_of_processor_hartid(dn, &hart); in of_parse_and_init_cpus()
134 if (hart == cpuid_to_hartid_map(0)) { in of_parse_and_init_cpus()
142 cpuid, hart); in of_parse_and_init_cpus()
146 cpuid_to_hartid_map(cpuid) = hart; in of_parse_and_init_cpus()
[all …]
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| D | machine_kexec.c | 107 * No more interrupts on this hart in machine_shutdown()
169 * suspended and this hart will be the new boot hart.
193 pr_notice("Will call new kernel at %08lx from hart id %lx\n", in machine_kexec()
197 /* Make sure the relocation code is visible to the hart */ in machine_kexec()
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| D | sys_riscv.c | 49 * kernel might schedule a process on another hart. There is no way for
51 * thread->hart mappings), so we've defined a RISC-V specific system call to
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| D | head.S | 174 * Park this hart if we:
249 /* Pick one hart to run the main boot sequence */
347 * This hart didn't win the lottery, so we wait for the winning hart to
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| /linux-6.12.1/Documentation/devicetree/bindings/iio/addac/ |
| D | adi,ad74115.yaml | 70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
[all …]
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| /linux-6.12.1/arch/riscv/mm/ |
| D | cacheflush.c | 39 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
42 * execution resumes on each hart.
51 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
54 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
68 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
69 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
71 * messages are sent we still need to order this hart's writes in flush_icache_mm()
166 * Mark every other hart's icache as needing a flush for in set_icache_stale_mask()
210 * process is migrated, the corresponding hart's icache will be guaranteed to be
219 * instructions. When the thread is migrated, the corresponding hart's icache
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| D | context.c | 241 * we polluted the TLB of current HART so let's do TLB flushed in asids_init()
289 * behavior in a common case (a bunch of single-hart processes on a many-hart
292 * cache flush to be performed before execution resumes on each hart. This
294 * refers to the current hart.
304 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-riscv-intc.c | 48 * on the local hart, these functions can only be called on the hart that
97 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
99 * chained handlers for the per-HART local interrupts. in riscv_intc_irq_eoi()
103 * will do unnecessary mask/unmask of per-HART local interrupts in riscv_intc_irq_eoi()
218 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
223 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
226 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
368 * The ACPI MADT will have one INTC for each CPU (or HART) in riscv_intc_acpi_init()
371 * for the INTC belonging to the boot CPU (or boot HART). in riscv_intc_acpi_init()
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| D | irq-riscv-aplic-msi.c | 103 /* Compute target HART Base PPN */ in aplic_msi_write_msg()
110 /* Compute target group and hart indexes */ in aplic_msi_write_msg()
212 /* Find number of HART index bits (LHXW) */ in aplic_msi_setup()
215 dev_err(dev, "IMSIC hart index bits big for APLIC LHXW\n"); in aplic_msi_setup()
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| /linux-6.12.1/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 18 hart: A hardware execution context, which contains all the state
62 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart.
68 this hart. These values originate from the RISC-V Privileged
81 The hart ID of this CPU node.
114 by this hart (see ./idle-states.yaml).
190 // Example 2: Spike ISA Simulator with 1 Hart
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| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,imsics.yaml | 17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
33 privilege level (machine or supervisor) encodes group index, HART index,
36 XLEN-1 > (HART Index MSB) 12 0
39 |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
76 HART) as parent.
101 riscv,hart-index-bits:
105 Number of HART index bits in the MSI target address. When not
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| D | riscv,cpu-intc.yaml | 7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
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| D | sifive,plic-1.0.0.yaml | 14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
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| /linux-6.12.1/Documentation/arch/riscv/ |
| D | cmodx.rst | 14 applications. At any point the scheduler may migrate a task onto a new hart. If
16 storage with fence.i, the icache on the new hart will no longer be clean. This
17 is due to the behavior of fence.i only affecting the hart that it is called on.
18 Thus, the hart that the task has been migrated to may not have synchronized
29 when the memory map being used by a hart changes. If the prctl() context caused
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| D | uabi.rst | 45 "isa" and "hart isa" lines in /proc/cpuinfo
50 "hart isa" line, in contrast, describes the set of extensions recognized by the
51 kernel on the particular hart being described, even if those extensions may not
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| /linux-6.12.1/arch/riscv/include/asm/ |
| D | cpu_ops_sbi.h | 16 * struct sbi_hart_boot_data - Hart specific boot used during booting and
18 * @task_ptr: A pointer to the hart specific tp
19 * @stack_ptr: A pointer to the hart specific sp
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| D | smp.h | 57 /* Secondary hart entry */
61 * Obtains the hart ID of the currently executing task. This relies on
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| /linux-6.12.1/arch/csky/abiv2/ |
| D | cacheflush.c | 47 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
71 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
75 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
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| /linux-6.12.1/tools/testing/selftests/futex/ |
| D | run.sh | 13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
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| /linux-6.12.1/tools/arch/riscv/include/uapi/asm/ |
| D | unistd.h | 29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
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| /linux-6.12.1/include/linux/irqchip/ |
| D | riscv-imsic.h | 53 * |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
57 /* Bits representing Guest index, HART index, and Group index */
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| /linux-6.12.1/tools/testing/selftests/futex/functional/ |
| D | run.sh | 12 # Darren Hart <dvhart@linux.intel.com>
15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
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| /linux-6.12.1/tools/testing/selftests/futex/include/ |
| D | atomic.h | 11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>
|